Datasheet ADSP-BF538, ADSP-BF538F (Analog Devices) - 2
| Fabricante | Analog Devices |
| Descripción | Blackfin Embedded Processor |
| Páginas / Página | 60 / 2 — ADSP-BF538/. ADSP-BF538F. TABLE OF CONTENTS. REVISION HISTORY. 11/13—Rev. … |
| Revisión | E |
| Formato / tamaño de archivo | PDF / 3.5 Mb |
| Idioma del documento | Inglés |
ADSP-BF538/. ADSP-BF538F. TABLE OF CONTENTS. REVISION HISTORY. 11/13—Rev. D to Rev. E
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ADSP-BF538/ ADSP-BF538F TABLE OF CONTENTS
Features ... 1 Clock Signals .. 14 Memory .. 1 Booting Modes ... 16 Peripherals ... 1 Instruction Set Description .. 16 General Description ... 3 Development Tools .. 16 Low Power Architecture ... 3 Additional Information .. 18 System Integration .. 3 Related Signal Chains ... 18 ADSP-BF538/ADSP-BF538F Processor Peripherals ... 3 Pin Descriptions .. 19 Blackfin Processor Core .. 4 Specifications .. 23 Memory Architecture .. 5 Operating Conditions ... 23 DMA Controllers .. 8 Electrical Characteristics ... 25 Real-Time Clock ... 9 Absolute Maximum Ratings ... 27 Watchdog Timer .. 9 ESD Sensitivity ... 27 Timers ... 9 Package Information .. 27 Serial Ports (SPORTs) .. 10 Timing Specifications ... 28 Serial Peripheral Interface (SPI) Ports .. 10 Output Drive Currents ... 47 2-Wire Interface ... 10 Test Conditions .. 49 UART Ports .. 11 Thermal Characteristics .. 53 General-Purpose Ports ... 11 316-Ball CSP_BGA Ball Assignment ... 54 Parallel Peripheral Interface ... 11 Outline Dimensions .. 57 Controller Area Network (CAN) Interface .. 12 Surface-Mount Design .. 57 Dynamic Power Management .. 13 Ordering Guide ... 58 Voltage Regulation .. 14
REVISION HISTORY 11/13—Rev. D to Rev. E
Updated Development Tools .. 16 Added footnote 3 to Operating Conditions .. 23 Updated Table 33 in Serial Port Timing ... 38 Added Timer Clock Timing .. 44 Added missing timing specifications to Table 39 in Timer Cycle Timing ... 45 Rev. E | Page 2 of 60 | November 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF538/ADSP-BF538F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF538F8 Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports General-Purpose Ports Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide
ADSP-BF538/ ADSP-BF538F TABLE OF CONTENTS
Features ... 1 Clock Signals .. 14 Memory .. 1 Booting Modes ... 16 Peripherals ... 1 Instruction Set Description .. 16 General Description ... 3 Development Tools .. 16 Low Power Architecture ... 3 Additional Information .. 18 System Integration .. 3 Related Signal Chains ... 18 ADSP-BF538/ADSP-BF538F Processor Peripherals ... 3 Pin Descriptions .. 19 Blackfin Processor Core .. 4 Specifications .. 23 Memory Architecture .. 5 Operating Conditions ... 23 DMA Controllers .. 8 Electrical Characteristics ... 25 Real-Time Clock ... 9 Absolute Maximum Ratings ... 27 Watchdog Timer .. 9 ESD Sensitivity ... 27 Timers ... 9 Package Information .. 27 Serial Ports (SPORTs) .. 10 Timing Specifications ... 28 Serial Peripheral Interface (SPI) Ports .. 10 Output Drive Currents ... 47 2-Wire Interface ... 10 Test Conditions .. 49 UART Ports .. 11 Thermal Characteristics .. 53 General-Purpose Ports ... 11 316-Ball CSP_BGA Ball Assignment ... 54 Parallel Peripheral Interface ... 11 Outline Dimensions .. 57 Controller Area Network (CAN) Interface .. 12 Surface-Mount Design .. 57 Dynamic Power Management .. 13 Ordering Guide ... 58 Voltage Regulation .. 14
REVISION HISTORY 11/13—Rev. D to Rev. E
Updated Development Tools .. 16 Added footnote 3 to Operating Conditions .. 23 Updated Table 33 in Serial Port Timing ... 38 Added Timer Clock Timing .. 44 Added missing timing specifications to Table 39 in Timer Cycle Timing ... 45 Rev. E | Page 2 of 60 | November 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF538/ADSP-BF538F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF538F8 Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports General-Purpose Ports Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide