Datasheet ADSP-BF522C, ADSP-BF523C, ADSP-BF524C, ADSP-BF525C, ADSP-BF526C, ADSP-BF527C (Analog Devices) - 4

link to page 4 link to page 30 link to page 5 ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C To allow an external device to generate the central reference
ANALOG AUDIO INTERFACES
clock, apply the external clock signal directly through the XTI/ The codec includes stereo single-ended line inputs and a mon- CODEC_MCLK input pin. In this configuration, the oscillator aural microphone input to the on-board ADC. Either the line circuit of the codec can be powered down by using the OSCPD inputs or the microphone input, but not both simultaneously, bit (Register R6, Bit D5) to reduce power consumption. can be connected to the ADC by setting the INSEL bit (Register To accommodate applications with very high frequency master R4, Bit D2). clocks, the internal core reference clock of the codec can be set The codec also includes line and headphone outputs from the to either CODEC_MCLK or CODEC_MCLK divided by 2. This on-board DAC. The line or microphone inputs can be routed is enabled by adjusting the setting of the CLKDIV2 bit (Register and mixed directly to the output terminals. R8, Bit D6). The CODEC_CLKOUT pin can also drive external clock sources with either the codec clock signal or codec clock
Stereo Line and Monaural Microphone Inputs
divided by 2 by enabling the CLKODIV2 bit (Register R8, Bit D7). The single-ended stereo line inputs (RLINEIN and LLINEIN) are internally biased to VMID by way of a voltage divider
ADC AND DAC
between AVDD and AGND (see Figure 2). The line input signal can be connected to the internal ADC and, if desired, routed The codec contains a pair of oversampling Σ-Δ ADCs. The directly to the outputs via the bypass path by using the BYPASS maximum ADC full-scale input level is 1.0 Vrms when bit (Register R4, Bit D3). AVDD = 3.3 V. If the input signal to the ADC exceeds this level, data overloading occurs and causes audible distortion. The ADC can accept analog audio input from either the stereo
RLINEIN or
line inputs or the monaural microphone input. Note that the
LLINEIN
ADC can only accept input from a single source, so the pro-
AVDD
grammer must choose either the line inputs or the microphone input using the INSEL bit (Register R4, Bit D2). The digital data
–
from the ADC output, once converted, is processed using the
ADC OR
ADC filters.
+ BYPASS VMID
Complementary to the Σ-Δ ADC channels, the codec contains a pair of oversampling DACs that convert the digital audio data
INTERNAL CIRCUITRY
from the internal DAC filters into an analog audio signal. The
AGND
DAC output can also be muted by setting the DACMU bit (Reg- ister R5, Bit D3) in the control register. Figure 2. Line Input to ADC
ADC HIGH-PASS AND DAC DE-EMPHASIS FILTERS
The line input volume can be adjusted from –34.5 dB to +33 dB in steps of +1.5 dB by setting the LINVOL (Register R0, Bit D0 The ADC and DAC employ separate digital filters that perform to Bit D5) and RINVOL (Register R1, Bit D0 to Bit D5) bits. By 24-bit signal processing. The digital filters are used for both default the volume is independently adjustable for both right record and playback modes and are optimized for each individ- and left line inputs. However, if the LRINBOTH or RLINBOTH ual sampling rate used. bit is programmed, both LINVOL and RINVOL are loaded with For recording mode operations, the unprocessed data from the the same value. The programmer can also set the LINMUTE ADC enters the ADC filters and is converted to the appropriate (Register R0, Bit D7) and RINMUTE (Register R1, Bit D7) bits sampling frequency, then is output to the digital audio interface. to mute the line input signal to the ADC. For playback mode operations, the DAC filters convert the digi- The high impedance, low capacitance monaural microphone tal audio interface data to oversampled data using a sampling input pin (MICIN, shown in Figure 3 ) has two gain stages and a rate selected by the programmer. The oversampled data is pro- microphone bias level (MICBIAS) that is internally biased to the cessed by the DAC and sent to the analog output mixer by VMID voltage level by way of a voltage divider between AVDD enabling the DACSEL (Register R4, Bit D4). and AGND. The microphone input signal can be connected to Programmers have the option of setting up the device so that the internal ADC and, if desired, routed directly to the outputs any dc offset in the input source signal is automatically detected via the sidetone path by using the SIDETONE bit (Register R4, and removed. To accomplish this, enable the digital high-pass Bit D5). filter (see Table 22 on Page 30 for characteristics) contained in the ADC digital filters by using the ADCHPD bit (Register R5, Bit D0). In addition, programmers can implement digital de-emphasis by using the DEEMPH bits (Register R5, Bit D1 and Bit D2). Rev. A | Page 4 of 36 | March 2010 Document Outline Blackfin Embedded Processor with Codec Processor Features Embedded Codec Features Peripherals Table of Contents Revision History General Description Codec Description ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Analog Audio Interfaces Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Normal Mode USB Mode Software Control Interface Codec Pin Descriptions Register Details Bit Descriptions Specifications Operating Conditions Codec Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Power Consumption Timing Specifications TWI Timing SPI Timing Digital Audio Interface Slave Mode Timing Digital Audio Interface Master Mode Timing System Clock Timing Digital Filter Characteristics Converter Filter Response Digital De-Emphasis 289-Ball CSP_BGA Ball Assignment Outline Dimensions Ordering Guide