Datasheet ADSP-BF522C, ADSP-BF523C, ADSP-BF524C, ADSP-BF525C, ADSP-BF526C, ADSP-BF527C (Analog Devices)

Blackfin Embedded Processor with Codec ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
PROCESSOR FEATURES EMBEDDED CODEC FEATURES Up to 600 MHz high performance Blackfin processor Stereo, 24-bit ADCs and DACs RISC-like register and instruction model for ease of DAC SNR: 100 dB (A-weighted), THD: –80 dB at 48 kHz, 3.3 V programming and compiler-friendly support ADC SNR: 90 dB (A-weighted), THD: –80 dB at 48 kHz, 3.3 V Advanced debug, trace, and performance monitoring Highly efficient headphone amplifier Accepts a wide range of supply voltages for internal and I/O Stereo line input and monaural microphone input operations. See operating conditions in the published Low power ADSP-BF52x processor data sheet. 7 mW stereo playback (1.8 V supply) Programmable on-chip voltage regulator (ADSP-BF523/ 14 mW record and playback (1.8 V supply) ADSP-BF525/ADSP-BF527processors only) Low supply voltages Embedded low power audio codec Analog: 1.8 V to 3.6 V 289-ball (12 mm x 12 mm) CSP_BGA package Digital core: 1.8 V min 132K bytes of on-chip memory Digital I/O: 1.8 V to 3.6 V External memory controller with glueless support for SDRAM 256 × fS /384 × fS oversampling rate in normal mode; and asynchronous 8-bit and 16-bit memories 250 × fS/272 × fS oversampling rate in USB mode Flexible booting options from external flash, SPI and TWI Audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, memory or from host devices including SPI, TWI, and UART 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, Code security with Lockbox Secure Technology and 96 kHz one-time-programmable (OTP) memory PERIPHERALS Memory management unit providing memory protection 2 dual-channel memory DMA controllers See the published ADSP-BF52x processor data sheet for additional peripherals WATCHDOG TIMER OTP MEMORY RTC VOLTAGE REGULATOR* JTAG TEST AND EMULATION COUNTER PERIPHERAL SPORT0 ACCESS BUS SPORT1 INTERRUPT GPIO
B
CONTROLLER UART1 PORT F UART0 L1 INSTRUCTION NFC L1 DATA DMA GPIO MEMORY MEMORY CONTROLLER DMA PPI PORT G ACCESS EAB 16 SPI CODEC BUS DCB USB TIMER7-1 GPIO DEB PORT H TIMER0 EXTERNAL PORT BOOT EMAC FLASH, SDRAM CONTROL ROM HOST DMA TWI PORT J *REGULATOR AVAILABLE ON ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS ONLY
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Document Outline Blackfin Embedded Processor with Codec Processor Features Embedded Codec Features Peripherals Table of Contents Revision History General Description Codec Description ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Analog Audio Interfaces Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Normal Mode USB Mode Software Control Interface Codec Pin Descriptions Register Details Bit Descriptions Specifications Operating Conditions Codec Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Power Consumption Timing Specifications TWI Timing SPI Timing Digital Audio Interface Slave Mode Timing Digital Audio Interface Master Mode Timing System Clock Timing Digital Filter Characteristics Converter Filter Response Digital De-Emphasis 289-Ball CSP_BGA Ball Assignment Outline Dimensions Ordering Guide