Datasheet LTM4623 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | Ultrathin 20VIN, 3A Step-Down DC/DC µModule Regulator |
| Páginas / Página | 28 / 7 — PACKAGE ROW AND COLUMN LABELING MAY VARY. SGND (B4):. AMONG µModule … |
| Revisión | D |
| Formato / tamaño de archivo | PDF / 305 Kb |
| Idioma del documento | Inglés |
PACKAGE ROW AND COLUMN LABELING MAY VARY. SGND (B4):. AMONG µModule PRODUCTS. REVIEW EACH PACKAGE. LAYOUT CAREFULLY. COMP (A1):
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LTM4623 PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY SGND (B4):
Signal Ground Connection. Tie to GND with
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
minimum distance. Connect FREQ resistor, COMP com-
LAYOUT CAREFULLY.
ponent, MODE, TRACK/SS component, FB resistor to this
COMP (A1):
Current Control Threshold and Error Amplifier pin as needed. Compensation Point. The current comparator’s trip thresh-
V
old is linearly proportional to this voltage, whose normal
OUT (C1, D1-D2, E1-E2):
Power Output Pins. Apply out- put load between these pins and GND pins. Recommend range is from 0.3V to 1.8V. Tie the COMP pins together for placing output decoupling capacitance directly between parallel operation. The device is internally compensated. these pins and GND pins. This is an output pin. Do not force a voltage on this pin.
PGOOD (C2):
Output Power Good with Open-Drain Logic.
TRACK/SS (A2):
Output Tracking and Soft-Start Input. PGOOD is pulled to ground when the voltage on the FB pin Allows the user to control the rise time of the output volt- is not within ±10% of the internal 0.6V reference. age. Putting a voltage below 0.6V on this pin bypasses the internal reference input to the error amplifier, and servos
MODE (C4):
Operation Mode Select. Tie this pin to INTVCC the FB pin to match the TRACK/SS voltage. Above 0.6V, to force continuous synchronous operation at all output the tracking function stops and the internal reference loads. Tying it to SGND enables discontinuous mode resumes control of the error amplifier. There’s an internal operation at light loads. Do not leave floating. 2µA pull-up current from INTVCC on this pin, so putting a
SV
capacitor here provides a soft-start function.
IN (C5):
Signal VIN. Input voltage to the on-chip 3.3V regulator. Tie this pin to the VIN pin in most applications.
RUN (A3):
Run Control Input of the Switching Mode Otherwise connect SVIN to an external voltage supply of Regulator. Enables chip operation by tying RUN above at least 4V which must also be greater than VOUT. 1.2V. Pulling it below 1.1V shuts down the part. Do not
V
leave floating.
IN (D5, E5):
Power Input Pins. Apply input voltage be- tween these pins and GND pins. Recommend placing
FREQ (A4):
Frequency is set internally to 1MHz. An ex- input decoupling capacitance directly between VIN pins ternal resistor can be placed from this pin to SGND to and GND pins. increase frequency, or from this pin to INTVCC to reduce
INTV
frequency. See the Applications Information section for
CC (E4):
Internal 3.3V Regulator Output. The internal power drivers and control circuits are powered from this frequency adjustment. voltage. This pin is internally decoupled to GND with a
FB (B1):
The Negative Input of the Error Amplifier. Internally, 1µF low ESR ceramic capacitor. this pin is connected to VOUT with a 60.4k precision resis-
CLKIN (A5):
External Synchronization Input to Phase tor. Different output voltages can be programmed with an Detector of the Switching Mode Regulator. This pin is additional resistor between the FB and SGND pins. Tying internally terminated to SGND with 20k. The phase-locked the FB pins together allows for parallel operation. See the loop will force the top power NMOS’s turn-on signal to Applications Information section for details. be synchronized with the rising edge of the CLKIN signal.
PHMODE (B2):
Control Input to Phase Selector of the
CLKOUT (B5):
Output Clock Signal for PolyPhase Op- Switching Mode Regulator Channel. This pin determines eration of the Switching Mode Regulator. The phase of the phase relationship between internal oscillator and CLKOUT with respect to CLKIN is determined by the state CLKOUT signal. Tie it to INTVCC for 2-phase operation, tie of the PHMODE pin. CLKOUT’s peak-to-peak amplitude it to SGND for 3-phase operation, and tie it to INTVCC/2 is INTV for 4-phase operation. CC to GND. This is an output pin. Do not force a voltage on this pin.
GND (B3, C3, D3-D4, E3):
Power Ground Pins for Both Input and Output Returns. Rev D For more information www.analog.com 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Revision History Package Photos Design Resources Related Parts
PACKAGE ROW AND COLUMN LABELING MAY VARY SGND (B4):
Signal Ground Connection. Tie to GND with
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
minimum distance. Connect FREQ resistor, COMP com-
LAYOUT CAREFULLY.
ponent, MODE, TRACK/SS component, FB resistor to this
COMP (A1):
Current Control Threshold and Error Amplifier pin as needed. Compensation Point. The current comparator’s trip thresh-
V
old is linearly proportional to this voltage, whose normal
OUT (C1, D1-D2, E1-E2):
Power Output Pins. Apply out- put load between these pins and GND pins. Recommend range is from 0.3V to 1.8V. Tie the COMP pins together for placing output decoupling capacitance directly between parallel operation. The device is internally compensated. these pins and GND pins. This is an output pin. Do not force a voltage on this pin.
PGOOD (C2):
Output Power Good with Open-Drain Logic.
TRACK/SS (A2):
Output Tracking and Soft-Start Input. PGOOD is pulled to ground when the voltage on the FB pin Allows the user to control the rise time of the output volt- is not within ±10% of the internal 0.6V reference. age. Putting a voltage below 0.6V on this pin bypasses the internal reference input to the error amplifier, and servos
MODE (C4):
Operation Mode Select. Tie this pin to INTVCC the FB pin to match the TRACK/SS voltage. Above 0.6V, to force continuous synchronous operation at all output the tracking function stops and the internal reference loads. Tying it to SGND enables discontinuous mode resumes control of the error amplifier. There’s an internal operation at light loads. Do not leave floating. 2µA pull-up current from INTVCC on this pin, so putting a
SV
capacitor here provides a soft-start function.
IN (C5):
Signal VIN. Input voltage to the on-chip 3.3V regulator. Tie this pin to the VIN pin in most applications.
RUN (A3):
Run Control Input of the Switching Mode Otherwise connect SVIN to an external voltage supply of Regulator. Enables chip operation by tying RUN above at least 4V which must also be greater than VOUT. 1.2V. Pulling it below 1.1V shuts down the part. Do not
V
leave floating.
IN (D5, E5):
Power Input Pins. Apply input voltage be- tween these pins and GND pins. Recommend placing
FREQ (A4):
Frequency is set internally to 1MHz. An ex- input decoupling capacitance directly between VIN pins ternal resistor can be placed from this pin to SGND to and GND pins. increase frequency, or from this pin to INTVCC to reduce
INTV
frequency. See the Applications Information section for
CC (E4):
Internal 3.3V Regulator Output. The internal power drivers and control circuits are powered from this frequency adjustment. voltage. This pin is internally decoupled to GND with a
FB (B1):
The Negative Input of the Error Amplifier. Internally, 1µF low ESR ceramic capacitor. this pin is connected to VOUT with a 60.4k precision resis-
CLKIN (A5):
External Synchronization Input to Phase tor. Different output voltages can be programmed with an Detector of the Switching Mode Regulator. This pin is additional resistor between the FB and SGND pins. Tying internally terminated to SGND with 20k. The phase-locked the FB pins together allows for parallel operation. See the loop will force the top power NMOS’s turn-on signal to Applications Information section for details. be synchronized with the rising edge of the CLKIN signal.
PHMODE (B2):
Control Input to Phase Selector of the
CLKOUT (B5):
Output Clock Signal for PolyPhase Op- Switching Mode Regulator Channel. This pin determines eration of the Switching Mode Regulator. The phase of the phase relationship between internal oscillator and CLKOUT with respect to CLKIN is determined by the state CLKOUT signal. Tie it to INTVCC for 2-phase operation, tie of the PHMODE pin. CLKOUT’s peak-to-peak amplitude it to SGND for 3-phase operation, and tie it to INTVCC/2 is INTV for 4-phase operation. CC to GND. This is an output pin. Do not force a voltage on this pin.
GND (B3, C3, D3-D4, E3):
Power Ground Pins for Both Input and Output Returns. Rev D For more information www.analog.com 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Revision History Package Photos Design Resources Related Parts