Datasheet LTC3701 (Analog Devices) - 7

LTC3701
U OPERATIO (Refer to Functional Diagram) Main Control Loop
VIN or to a voltage of at least 2V. To disable Burst Mode operation and enable PWM pulse skipping mode, connect The LTC3701 uses a constant frequency, current mode the EXTCLK/MODE pin to ground. In this mode, the architecture with the two controller channels operating efficiency is lower at light loads. However, pulse skipping 180 degrees out of phase. During normal operation, each mode has the advantages of lower output ripple and less external P-channel power MOSFET is turned on when the interference to audio circuitry. clock for that channel sets the RS latch, and turned off when the current comparator (ICMP) resets the latch. The When a controller is in Burst Mode operation, the peak peak inductor current at which ICMP resets the RS latch is current of the inductor is set as if VITH/RUN = 1V, even controlled by the voltage on the ITH/RUN pin, which is the though the voltage at the ITH/RUN pin is at a lower value. output of each error amplifier, EAMP. The VFB pin receives If the inductor’s average current is greater than the load the voltage feedback signal, which is compared to the requirement, the voltage at the ITH/RUN pin will drop. internal reference voltage by the EAMP. When the load When the ITH/RUN voltage goes below 0.85V, the sleep current increases, it causes a slight decrease in VFB signal goes high, turning off the external MOSFET. The relative to the 0.8V reference, which in turn, causes the ITH/ sleep signal goes low when the ITH/RUN voltage goes RUN voltage to increase until the average inductor current above 0.925V and that controller channel resumes normal matches the new load current. operation. The next oscillator cycle will turn the external MOSFET on and the switching cycle repeats. Each main control loop is shut down by pulling the respective ITH/RUN pin low. When both ITH/RUN1 and ITH/
Frequency Synchronization
RUN2 are low, all LTC3701 controller functions are shut down. Releasing I A phase-locked loop (PLL) is available on the LTC3701 to TH/RUN allows an internal 0.5µA current source to charge up the external compensation network. allow the internal oscillator to be synchronized to an When the I external clock source connected to the EXTCLK/MODE TH/RUN pin reaches 0.35V, the main control loop is enabled with the I pin. The output of the phase detector at the PLLLPF pin TH/RUN voltage then pulled up to its zero current level of approximately 0.7V. After the loop operates over a 0V to 2.4V range corresponding to ap- is enabled, an internal soft-start begins. During this soft- proximately 300kHz to 750kHz. When locked, the PLL start time of 2048 clock cycles, the I aligns the turn-on of the external MOSFET of controller TH/RUN voltage is clamped such that the maximum peak current sense channel 1 to the rising edge of the synchronizing signal. voltage (V + – The turn-on of the external MOSFET of controller channel SENSE – VSENSE ) is held to approximately 0%, 25%, 50% and 75%, respectively, of its maximum value of 2 is 180 degrees out of phase with the rising edge of the 120mV for four equally timed intervals. After soft-start is external clock source. completed, full current operation is allowed. As the exter- When the LTC3701 is clocked by an external source, Burst nal compensation network continues to charge, the corre- Mode operation is disabled and the LTC3701 operates in sponding output current trip level follows, allowing normal PWM pulse skipping mode. In this mode, when the output operation. load is very low, the current comparator ICMP may remain Comparator OVP guards against transient output voltage tripped for several cycles and force the external MOSFET overshoots greater than 10% by turning off the external to stay off for the same number of cycles. Increasing the P-channel power MOSFET and keeping it off until the fault output load slightly allows constant frequency PWM op- is removed. eration to resume. This mode exhibits low output ripple as well as low audio noise and reduced RF interference while
Burst Mode Operation
providing reasonable low current efficiency. The LTC3701 can be enabled to enter Burst Mode opera- tion at low load currents by tying the EXTCLK/MODE pin to 3701fa 7