Datasheet LTC3701 (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | 2-Phase, Low Input Voltage, Dual Step-Down DC/DC Controller |
| Páginas / Página | 20 / 5 — PI FU CTIO S. SENSE1–, SENSE2– (Pins 1, 8):. EXTCLK/MODE (Pin 10):. … |
| Formato / tamaño de archivo | PDF / 261 Kb |
| Idioma del documento | Inglés |
PI FU CTIO S. SENSE1–, SENSE2– (Pins 1, 8):. EXTCLK/MODE (Pin 10):. ITH/RUN1, ITH/RUN2 (Pins 2, 6):. VFB1, VFB2 (Pins 3, 5):
Línea de modelo para esta hoja de datos
Versión de texto del documento
LTC3701
U U U PI FU CTIO S SENSE1–, SENSE2– (Pins 1, 8):
The (–) Inputs to the
EXTCLK/MODE (Pin 10):
External Clock Input. Applying a Differential Current Comparators. clock to this pin causes the internal oscillator to phase- lock to the external clock (nominal lock frequency range
ITH/RUN1, ITH/RUN2 (Pins 2, 6):
These pins each serve between 300kHz and 750kHz). This also disables Burst two functions. Each pin serves as the error amplifier Mode operation but allows pulse-skipping at low load compensation point as well as the run control input for the currents. respective controller. Forcing one pin below 0.35V causes the functions associated with that controller to be shut Forcing this pin high enables Burst Mode operation. down. Forcing both ITH/RUN pins below 0.35V causes the Forcing this pin low enables pulse-skipping mode. In device to be shut down. Nominal operating voltage range these cases, the frequency of the internal oscillator is set on these pins is from 0.7V to 1.9V. by the voltage on the PLLLPF pin. If the PLLLPF voltage is not set externally, the frequency internally defaults to
VFB1, VFB2 (Pins 3, 5):
Each receives the remotely sensed 550kHz. feedback voltage for each controller from an external resistive divider across the output.
PGOOD (Pin 11):
Power Good Output Voltage Monitor Open-Drain Logic Output. This pin is pulled to ground
SGND (Pin 4):
Signal Ground. when the voltage on either feedback pin (VFB1, VFB2) is not
PLLLPF (Pin 7):
Serves as the lowpass filter point for the within ±8% of its nominal set point. PGOOD is pulled low PLL and as the voltage control input to the internal when channel 1 or both channels are shut down. When oscillator. Normally, a series RC is connected between this channel 2 is shut down and channel 1 enabled, the pin and ground when synchronizing to an external clock. PGOOD output indicates the state of VFB1 only. Nominal voltage range is from 0V to 2.4V. Frequency can
PGATE2, PGATE1 (Pins 12, 14):
Gate Drivers for the be set by forcing this pin with a voltage. Tying this pin to External P-Channel MOSFETs. These pins swing from 0 to GND selects 300kHz. Tying to VIN or a voltage ≥ 2.4V SENSE+ (PV selects 750kHz. Floating this pin selects 550kHz opera- IN). tion.
PGND (Pin 13):
Ground Pin for Gate Drivers.
SENSE2+ (PVIN2), SENSE1+ (PVIN1) (Pins 9, 16):
The (+)
VIN (Pin 15):
Chip Signal Power Supply Input. This pin Inputs to the Differential Current Comparators. These pins powers the entire chip except for the gate drivers. also power the gate drivers. 3701fa 5
U U U PI FU CTIO S SENSE1–, SENSE2– (Pins 1, 8):
The (–) Inputs to the
EXTCLK/MODE (Pin 10):
External Clock Input. Applying a Differential Current Comparators. clock to this pin causes the internal oscillator to phase- lock to the external clock (nominal lock frequency range
ITH/RUN1, ITH/RUN2 (Pins 2, 6):
These pins each serve between 300kHz and 750kHz). This also disables Burst two functions. Each pin serves as the error amplifier Mode operation but allows pulse-skipping at low load compensation point as well as the run control input for the currents. respective controller. Forcing one pin below 0.35V causes the functions associated with that controller to be shut Forcing this pin high enables Burst Mode operation. down. Forcing both ITH/RUN pins below 0.35V causes the Forcing this pin low enables pulse-skipping mode. In device to be shut down. Nominal operating voltage range these cases, the frequency of the internal oscillator is set on these pins is from 0.7V to 1.9V. by the voltage on the PLLLPF pin. If the PLLLPF voltage is not set externally, the frequency internally defaults to
VFB1, VFB2 (Pins 3, 5):
Each receives the remotely sensed 550kHz. feedback voltage for each controller from an external resistive divider across the output.
PGOOD (Pin 11):
Power Good Output Voltage Monitor Open-Drain Logic Output. This pin is pulled to ground
SGND (Pin 4):
Signal Ground. when the voltage on either feedback pin (VFB1, VFB2) is not
PLLLPF (Pin 7):
Serves as the lowpass filter point for the within ±8% of its nominal set point. PGOOD is pulled low PLL and as the voltage control input to the internal when channel 1 or both channels are shut down. When oscillator. Normally, a series RC is connected between this channel 2 is shut down and channel 1 enabled, the pin and ground when synchronizing to an external clock. PGOOD output indicates the state of VFB1 only. Nominal voltage range is from 0V to 2.4V. Frequency can
PGATE2, PGATE1 (Pins 12, 14):
Gate Drivers for the be set by forcing this pin with a voltage. Tying this pin to External P-Channel MOSFETs. These pins swing from 0 to GND selects 300kHz. Tying to VIN or a voltage ≥ 2.4V SENSE+ (PV selects 750kHz. Floating this pin selects 550kHz opera- IN). tion.
PGND (Pin 13):
Ground Pin for Gate Drivers.
SENSE2+ (PVIN2), SENSE1+ (PVIN1) (Pins 9, 16):
The (+)
VIN (Pin 15):
Chip Signal Power Supply Input. This pin Inputs to the Differential Current Comparators. These pins powers the entire chip except for the gate drivers. also power the gate drivers. 3701fa 5