Datasheet LTC3727, LTC3727-1 (Analog Devices) - 10

FabricanteAnalog Devices
DescripciónHigh Efficiency, 2-Phase Synchronous Step-Down Switching Regulators
Páginas / Página32 / 10 — OPERATIO (Refer to Functional Diagram). Frequency Synchronization. …
Formato / tamaño de archivoPDF / 381 Kb
Idioma del documentoInglés

OPERATIO (Refer to Functional Diagram). Frequency Synchronization. Continuous Current (PWM) Operation. Low Current Operation

OPERATIO (Refer to Functional Diagram) Frequency Synchronization Continuous Current (PWM) Operation Low Current Operation

Línea de modelo para esta hoja de datos

Versión de texto del documento

LTC3727/LTC3727-1
U OPERATIO (Refer to Functional Diagram)
The top MOSFET drivers are biased from floating boot- having the hysteretic comparator follow the error ampli- strap capacitor CB, which normally is recharged during fier gain block. each off cycle through an external diode when the top MOSFET turns off. As V
Frequency Synchronization
IN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on The phase-locked loop allows the internal oscillator to be the top MOSFET continuously. The dropout detector de- synchronized to an external source via the PLLIN pin. The tects this and forces the top MOSFET off for about 400ns output of the phase detector at the PLLFLTR pin is also the every tenth cycle to allow CB to recharge. DC frequency control input of the oscillator that operates The main control loop is shut down by pulling the RUN/SS over a 250kHz to 550kHz range corresponding to a DC pin low. Releasing RUN/SS allows an internal 1.2μA voltage input from 0V to 2.4V. When locked, the PLL current source to charge soft-start capacitor C aligns the turn on of the top MOSFET to the rising edge of SS. When C the synchronizing signal. When PLLIN is left open, the SS reaches 1.5V, the main control loop is enabled with the I PLLFLTR pin goes low, forcing the oscillator to its mini- TH voltage clamped at approximately 30% of its maximum value. As C mum frequency. SS continues to charge, the ITH pin voltage is gradually released allowing normal, full-current opera- tion. When both RUN/SS1 and RUN/SS2 are low, all
Continuous Current (PWM) Operation
LTC3727/LTC3727-1 controller functions are shut down, Tying the FCB pin to ground will force continuous current including the 7.5V and 3.3V regulators. operation. This is the least efficient operating mode, but may be desirable in certain applications. The output can
Low Current Operation
source or sink current in this mode. When sinking current The FCB pin is a multifunction pin providing two func- while in forced continuous operation, current will be tions: 1) to provide regulation for a secondary winding by forced back into the main power supply potentially boost- temporarily forcing continuous PWM operation on ing the input supply to dangerous voltage levels— both controllers; and 2) to select between two modes of BEWARE! low current operation. When the FCB pin voltage is below 0.8V, the controller forces continuous PWM current
INTVCC/EXTVCC Power
mode operation. In this mode, the top and bottom Power for the top and bottom MOSFET drivers and most MOSFETs are alternately turned on to maintain the output other internal circuitry is derived from the INTVCC pin. voltage independent of direction of inductor current. When the EXTVCC pin is left open, an internal 7.5V low When the FCB pin is below VINTVCC – 2V but greater than dropout linear regulator supplies INTVCC power. If EXTVCC 0.8V, the controller enters Burst Mode operation. Burst is taken above 7.3V, the 7.5V regulator is turned off and an Mode operation sets a minimum output current level internal switch is turned on connecting EXTVCC to INTVCC. before inhibiting the top switch and turns off the synchro- This allows the INTVCC power to be derived from a high nous MOSFET(s) when the inductor current goes nega- efficiency external source such as the output of the regu- tive. This combination of requirements will, at low cur- lator itself or a secondary winding, as described in the rents, force the ITH pin below a voltage threshold that will Applications Information section. temporarily inhibit turn-on of both output MOSFETs until the output voltage drops. There is 60mV of hysteresis in
Output Overvoltage Protection
the burst comparator B tied to the ITH pin. This hysteresis An overvoltage comparator, OV, guards against transient produces output signals to the MOSFETs that turn them overshoots (>7.5%) as well as other more serious condi- on for several cycles, followed by a variable “sleep” tions that may overvoltage the output. In this case, the top interval depending upon the load current. The resultant MOSFET is turned off and the bottom MOSFET is turned on output voltage ripple is held to a very small value by until the overvoltage condition is cleared. 3727fc 10