Datasheet LTC3736-1 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | Dual 2-Phase, No RSENSE , Synchronous Controller with Spread Spectrum |
| Páginas / Página | 28 / 7 — PI FU CTIO S (UF/GN Package). TG1/TG2 (Pins 17, 15/Pins 20, 18):. SW1/SW2 … |
| Formato / tamaño de archivo | PDF / 541 Kb |
| Idioma del documento | Inglés |
PI FU CTIO S (UF/GN Package). TG1/TG2 (Pins 17, 15/Pins 20, 18):. SW1/SW2 (Pins 22, 10/Pins 1, 13):. SSDIS (Pin 18/Pin 21):
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LTC3736-1
U U U PI FU CTIO S (UF/GN Package) TG1/TG2 (Pins 17, 15/Pins 20, 18):
Top (PMOS) Gate Drive
SW1/SW2 (Pins 22, 10/Pins 1, 13):
Switch Node Connec- Output. These pins drive the gates of the external P-channel tion to Inductor. Also the negative input to differential peak MOSFETs. These pins have an output swing from PGND to current comparator and an input to the reverse current SENSE+. comparator. Normally connected to the drain of the exter-
SSDIS (Pin 18/Pin 21):
Spread Spectrum Disable Input. Tie nal P-channel MOSFETs, the drain of the external N-channel this pin to V MOSFET and the inductor. IN to disable spread spectrum operation. In this mode, the LTC3736-1 operates at a constant frequency
IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5):
Three-State Pins to determined by the voltage on the FREQ pin. Tie this pin to Select Maximum Peak Sense Voltage Threshold. These pins GND to enable spread spectrum operation. select the maximum allowed voltage drop between the
BG1/BG2 (Pins 19, 13/Pins 22, 16):
Bottom (NMOS) Gate SENSE+ and SW pins (i.e., the maximum allowed drop Drive Output. These pins drive the gates of the external N- across the external P-channel MOSFET) for each channel. channel MOSFETs. These pins have an output swing from Tie to VIN, GND or float to select 204mV, 85mV or 125mV PGND to SENSE+. respectively.
SENSE1+/SENSE2+ (Pins 21, 11/Pins 24, 14):
Positive
VFB1/VFB2 (Pins 24, 7/Pins 3, 10):
Feedback Pins. Receives Input to Differential Current Comparator. Also powers the the remotely sensed feedback voltage for its controller from gate drivers. Normally connected to the source of the ex- an external resistor divider across the output. ternal P-channel MOSFET.
Exposed Pad (Pin 25/NA):
The exposed pad (UF Package) must be soldered to the PCB ground.
U U W FU CTIO AL DIAGRA (Common Circuitry)
RVIN VIN (TO CONTROLLER 1, 2) VIN CVIN UNDERVOLTAGE VOLTAGE 0.6V LOCKOUT REFERENCE VREF 0.7µA SHDN RUN/SS tSEC = 1ms + EXTSS INTSS – SSDIS FREQ CLK1 SPREAD SLOPE1 SLOPE SPECTRUM CLK2 COMP OSCILLATOR SLOPE2 – VFB1 UV1 PGOOD OV1 + SHDN 0.54V IPRG1 VOLTAGE IPROG1 MAXIMUM + CONTROLLED OV2 37361 FD IPRG2 SENSE VOLTAGE UV2 OSCILLATOR SELECT IPROG2 VFB2 – 37361f 7
U U U PI FU CTIO S (UF/GN Package) TG1/TG2 (Pins 17, 15/Pins 20, 18):
Top (PMOS) Gate Drive
SW1/SW2 (Pins 22, 10/Pins 1, 13):
Switch Node Connec- Output. These pins drive the gates of the external P-channel tion to Inductor. Also the negative input to differential peak MOSFETs. These pins have an output swing from PGND to current comparator and an input to the reverse current SENSE+. comparator. Normally connected to the drain of the exter-
SSDIS (Pin 18/Pin 21):
Spread Spectrum Disable Input. Tie nal P-channel MOSFETs, the drain of the external N-channel this pin to V MOSFET and the inductor. IN to disable spread spectrum operation. In this mode, the LTC3736-1 operates at a constant frequency
IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5):
Three-State Pins to determined by the voltage on the FREQ pin. Tie this pin to Select Maximum Peak Sense Voltage Threshold. These pins GND to enable spread spectrum operation. select the maximum allowed voltage drop between the
BG1/BG2 (Pins 19, 13/Pins 22, 16):
Bottom (NMOS) Gate SENSE+ and SW pins (i.e., the maximum allowed drop Drive Output. These pins drive the gates of the external N- across the external P-channel MOSFET) for each channel. channel MOSFETs. These pins have an output swing from Tie to VIN, GND or float to select 204mV, 85mV or 125mV PGND to SENSE+. respectively.
SENSE1+/SENSE2+ (Pins 21, 11/Pins 24, 14):
Positive
VFB1/VFB2 (Pins 24, 7/Pins 3, 10):
Feedback Pins. Receives Input to Differential Current Comparator. Also powers the the remotely sensed feedback voltage for its controller from gate drivers. Normally connected to the source of the ex- an external resistor divider across the output. ternal P-channel MOSFET.
Exposed Pad (Pin 25/NA):
The exposed pad (UF Package) must be soldered to the PCB ground.
U U W FU CTIO AL DIAGRA (Common Circuitry)
RVIN VIN (TO CONTROLLER 1, 2) VIN CVIN UNDERVOLTAGE VOLTAGE 0.6V LOCKOUT REFERENCE VREF 0.7µA SHDN RUN/SS tSEC = 1ms + EXTSS INTSS – SSDIS FREQ CLK1 SPREAD SLOPE1 SLOPE SPECTRUM CLK2 COMP OSCILLATOR SLOPE2 – VFB1 UV1 PGOOD OV1 + SHDN 0.54V IPRG1 VOLTAGE IPROG1 MAXIMUM + CONTROLLED OV2 37361 FD IPRG2 SENSE VOLTAGE UV2 OSCILLATOR SELECT IPROG2 VFB2 – 37361f 7