Datasheet LTC3853 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | Triple Output, Multiphase Synchronous Step-Down Controller |
| Páginas / Página | 36 / 9 — PIN FUNCTIONS. RUN1, RUN2, RUN3 (Pins 36, 35, 34):. ILIM (Pin 39):. … |
| Formato / tamaño de archivo | PDF / 763 Kb |
| Idioma del documento | Inglés |
PIN FUNCTIONS. RUN1, RUN2, RUN3 (Pins 36, 35, 34):. ILIM (Pin 39):. TK/SS1, TK/SS2, TK/SS3 (Pins 40, 1, 2):
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LTC3853
PIN FUNCTIONS RUN1, RUN2, RUN3 (Pins 36, 35, 34):
Run Control In-
ILIM (Pin 39):
Current Comparator Sense Voltage Range puts. A voltage above 1.2V on any RUN pin turns on the Inputs. This pin is to be programmed to SGND, FLOAT or IC. However, forcing any of these pins below 1.2V causes INTVCC to set the maximum current sense threshold to the IC to shut down the circuitry required for that particular three different levels. channel. There are 0.5µA pull-up currents for these pins.
TK/SS1, TK/SS2, TK/SS3 (Pins 40, 1, 2):
Output Voltage Once the RUN pin rises above 1.2V, an additional 4.5µA Tracking and Soft-Start Inputs. When one particular channel pull-up current is added to the pin. is configured to be the master, a capacitor to ground at
MODE/PLLIN (Pin 37):
Force Continuous Mode, Burst this pin sets the ramp rate for the master channel’s output Mode, or Pulse Skip Mode Selection Pin and External voltage. When the channel is configured to be the slave, Synchronization Input to Phase Detector Pin. Connect the VFB voltage of the master channel is reproduced by a this pin to SGND to force all channels into the continuous resistor divider and applied to this pin. Internal soft-start mode of operation. Connect to INTVCC to enable pulse currents of 1.3µA are charging the soft-start capacitors. skip mode of operation. Leaving the pin floating will en- In dual output (2 + 1) mode, TK/SS1 and TK/SS2 need to able Burst Mode operation. A clock on the pin will force be shorted externally. the controller into continuous mode of operation and
PGND (Exposed Pad Pin 41):
Power Ground. Connect this synchronize the internal oscillator. pin close to the sources of the bottom N-channel MOSFETs,
FREQ/PLLFLTR (Pin 38):
The phase-locked loop’s low- the (–) terminal of CVCC and the (–) terminal of CIN. pass filter is tied to this pin. Alternatively, this pin can be driven with a DC voltage to vary the frequency of the internal oscillator. 3853fc For more information www.linear.com/LTC3853 9 Document Outline Features Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS RUN1, RUN2, RUN3 (Pins 36, 35, 34):
Run Control In-
ILIM (Pin 39):
Current Comparator Sense Voltage Range puts. A voltage above 1.2V on any RUN pin turns on the Inputs. This pin is to be programmed to SGND, FLOAT or IC. However, forcing any of these pins below 1.2V causes INTVCC to set the maximum current sense threshold to the IC to shut down the circuitry required for that particular three different levels. channel. There are 0.5µA pull-up currents for these pins.
TK/SS1, TK/SS2, TK/SS3 (Pins 40, 1, 2):
Output Voltage Once the RUN pin rises above 1.2V, an additional 4.5µA Tracking and Soft-Start Inputs. When one particular channel pull-up current is added to the pin. is configured to be the master, a capacitor to ground at
MODE/PLLIN (Pin 37):
Force Continuous Mode, Burst this pin sets the ramp rate for the master channel’s output Mode, or Pulse Skip Mode Selection Pin and External voltage. When the channel is configured to be the slave, Synchronization Input to Phase Detector Pin. Connect the VFB voltage of the master channel is reproduced by a this pin to SGND to force all channels into the continuous resistor divider and applied to this pin. Internal soft-start mode of operation. Connect to INTVCC to enable pulse currents of 1.3µA are charging the soft-start capacitors. skip mode of operation. Leaving the pin floating will en- In dual output (2 + 1) mode, TK/SS1 and TK/SS2 need to able Burst Mode operation. A clock on the pin will force be shorted externally. the controller into continuous mode of operation and
PGND (Exposed Pad Pin 41):
Power Ground. Connect this synchronize the internal oscillator. pin close to the sources of the bottom N-channel MOSFETs,
FREQ/PLLFLTR (Pin 38):
The phase-locked loop’s low- the (–) terminal of CVCC and the (–) terminal of CIN. pass filter is tied to this pin. Alternatively, this pin can be driven with a DC voltage to vary the frequency of the internal oscillator. 3853fc For more information www.linear.com/LTC3853 9 Document Outline Features Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts