Datasheet LTC3860 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | Dual, Multiphase Step-Down Voltage Mode DC/DC Controller with Current Sharing |
| Páginas / Página | 36 / 8 — PIN FUNCTIONS. VCC (Pin 1):. ISNS1N (Pin 21), ISNS2N (Pin 20):. FB1 (Pin … |
| Formato / tamaño de archivo | PDF / 451 Kb |
| Idioma del documento | Inglés |
PIN FUNCTIONS. VCC (Pin 1):. ISNS1N (Pin 21), ISNS2N (Pin 20):. FB1 (Pin 2), FB2 (Pin 8):. ISNS1P (Pin 22), ISNS2P (Pin 19):
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LTC3860
PIN FUNCTIONS VCC (Pin 1):
Chip Supply Voltage. Bypass this pin to GND
ISNS1N (Pin 21), ISNS2N (Pin 20):
Current Sense Am- with a capacitor (0.1μF to 1μF ceramic) in close proximity plifi er (–) Input. The (–) input to the current amplifi er is to the chip. normally connected to the respective VOUT.
FB1 (Pin 2), FB2 (Pin 8):
Error Amplifi er Inverting Inputs.
ISNS1P (Pin 22), ISNS2P (Pin 19):
Current Sense Amplifi er FB1 or FB2 can be connected to VSNSOUT via a resistor (+) Input. The (+) input to the current sense amplifi er is divider for remote VOUT sensing. The bottom of the divider normally connected to the midpoint of the inductor’s parallel should be connected to the SGND pin of the IC. The other RC sense circuit or to the node between the inductor and FB, when used, is typically connected to the other VOUT via sense resistor if using a discrete sense resistor. a resistor divider, also terminated at the IC SGND pin.
ILIM1 (Pin 23), ILIM2 (Pin 18):
Current Comparator Sense
COMP1 (Pin 3), COMP2 (Pin 7):
Error Amplifi er Outputs. Voltage Limit Selection Pin. Connect a resistor from this PWM duty cycle increases with this control voltage. pin to SGND. This pin sources 20μA. The resultant voltage The error amplifi ers in the LTC3860 are true operational sets the threshold for overcurrent protection. amplifi ers with low output impedance. As a result, the
RUN1 (Pin 24), RUN2 (Pin 17):
Run Control Inputs. A outputs of two active error amplifi ers cannot be directly voltage above 2.25V on either pin turns on the IC. How- connected together! For multiphase operation, connecting ever, forcing either of these pins below 2V causes the IC the FB pin on an error amplifi er to VCC will three-state to shut down that particular channel. There are 1.5μA the output of that amplifi er. Multiphase operation can pull-up currents for these pins. then be achieved by connecting all of the COMP pins together and using one channel as the master and all
PWM1 (Pin 25), PWM2 (Pin 16):
(Top) Gate Signal Out- others as slaves. put. This signal goes to the PWM or top gate input of the external gate driver or integrated driver MOSFET. This is
VSNSOUT (Pin 4):
Differential Amplifi er Output. a three-state compatible output.
VSNSN (Pin 5):
Remote Sense Differential Amplifi er
PWMEN1/PWMEN2 (Pin 26/Pin 15):
Enable Pin for Non- Inverting Input. Connect this pin to sense ground at the Three-State compatible drivers. This pin has an internal output load. open-drain pull-up to VCC. An external resistor to SGND
VSNSP (Pin 6):
Remote Sense Differential Amplifi er is required. This pin is low when the corresponding PWM Noninverting Input. Connect this pin to VOUT at the output pin is high impedance. load.
PGOOD1 (Pin 27), PGOOD2 (Pin 14):
Power Good Pins.
FREQ (Pin 10):
Frequency Set/Select Pin. If CLKIN is high, Open-drain outputs that pull to ground when output volt- the resistor between this pin and SGND sets the switching age is not in regulation. frequency. If CLKIN is low, the logic state of this pin sets
I
frequency. This pin sources 21μA.
AVG (Pin 28):
Average Current Output Pin. A capacitor tied to ground from this pin stores a voltage proportional to
CLKIN (Pin 11):
External Clock Synchronization Input the master’s instantaneous average current when multiple Pin. If an external clock is present at this pin, the switch- outputs are paralleled. Tie the IAVG pin to ground when the ing frequency will be synchronized to the external clock. controller drives two independent outputs. Otherwise, if high, a resistor from FREQ to SGND sets
SGND (Pins 29, 30, Exposed Pad Pin 33):
Ground. Pins frequency; if low, FREQ state sets frequency. 29, 30 and 33 are electrically connected internally. The
CLKOUT (Pin 12):
Clock Output Pin. Used to synchronize exposed pad must be soldered to the PCB for rated thermal other LTC3860s. performance.
PHSMD (Pin 13):
Phase Mode Pin. Selects Ch1-Ch2 and
VINSNS (Pin 31):
VIN Sense Pin. Connects to the VIN Ch1-CLKOUT phase relationship. power supply to provide line feedforward compensation. 3860fc 8 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL DIAGRAM OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
PIN FUNCTIONS VCC (Pin 1):
Chip Supply Voltage. Bypass this pin to GND
ISNS1N (Pin 21), ISNS2N (Pin 20):
Current Sense Am- with a capacitor (0.1μF to 1μF ceramic) in close proximity plifi er (–) Input. The (–) input to the current amplifi er is to the chip. normally connected to the respective VOUT.
FB1 (Pin 2), FB2 (Pin 8):
Error Amplifi er Inverting Inputs.
ISNS1P (Pin 22), ISNS2P (Pin 19):
Current Sense Amplifi er FB1 or FB2 can be connected to VSNSOUT via a resistor (+) Input. The (+) input to the current sense amplifi er is divider for remote VOUT sensing. The bottom of the divider normally connected to the midpoint of the inductor’s parallel should be connected to the SGND pin of the IC. The other RC sense circuit or to the node between the inductor and FB, when used, is typically connected to the other VOUT via sense resistor if using a discrete sense resistor. a resistor divider, also terminated at the IC SGND pin.
ILIM1 (Pin 23), ILIM2 (Pin 18):
Current Comparator Sense
COMP1 (Pin 3), COMP2 (Pin 7):
Error Amplifi er Outputs. Voltage Limit Selection Pin. Connect a resistor from this PWM duty cycle increases with this control voltage. pin to SGND. This pin sources 20μA. The resultant voltage The error amplifi ers in the LTC3860 are true operational sets the threshold for overcurrent protection. amplifi ers with low output impedance. As a result, the
RUN1 (Pin 24), RUN2 (Pin 17):
Run Control Inputs. A outputs of two active error amplifi ers cannot be directly voltage above 2.25V on either pin turns on the IC. How- connected together! For multiphase operation, connecting ever, forcing either of these pins below 2V causes the IC the FB pin on an error amplifi er to VCC will three-state to shut down that particular channel. There are 1.5μA the output of that amplifi er. Multiphase operation can pull-up currents for these pins. then be achieved by connecting all of the COMP pins together and using one channel as the master and all
PWM1 (Pin 25), PWM2 (Pin 16):
(Top) Gate Signal Out- others as slaves. put. This signal goes to the PWM or top gate input of the external gate driver or integrated driver MOSFET. This is
VSNSOUT (Pin 4):
Differential Amplifi er Output. a three-state compatible output.
VSNSN (Pin 5):
Remote Sense Differential Amplifi er
PWMEN1/PWMEN2 (Pin 26/Pin 15):
Enable Pin for Non- Inverting Input. Connect this pin to sense ground at the Three-State compatible drivers. This pin has an internal output load. open-drain pull-up to VCC. An external resistor to SGND
VSNSP (Pin 6):
Remote Sense Differential Amplifi er is required. This pin is low when the corresponding PWM Noninverting Input. Connect this pin to VOUT at the output pin is high impedance. load.
PGOOD1 (Pin 27), PGOOD2 (Pin 14):
Power Good Pins.
FREQ (Pin 10):
Frequency Set/Select Pin. If CLKIN is high, Open-drain outputs that pull to ground when output volt- the resistor between this pin and SGND sets the switching age is not in regulation. frequency. If CLKIN is low, the logic state of this pin sets
I
frequency. This pin sources 21μA.
AVG (Pin 28):
Average Current Output Pin. A capacitor tied to ground from this pin stores a voltage proportional to
CLKIN (Pin 11):
External Clock Synchronization Input the master’s instantaneous average current when multiple Pin. If an external clock is present at this pin, the switch- outputs are paralleled. Tie the IAVG pin to ground when the ing frequency will be synchronized to the external clock. controller drives two independent outputs. Otherwise, if high, a resistor from FREQ to SGND sets
SGND (Pins 29, 30, Exposed Pad Pin 33):
Ground. Pins frequency; if low, FREQ state sets frequency. 29, 30 and 33 are electrically connected internally. The
CLKOUT (Pin 12):
Clock Output Pin. Used to synchronize exposed pad must be soldered to the PCB for rated thermal other LTC3860s. performance.
PHSMD (Pin 13):
Phase Mode Pin. Selects Ch1-Ch2 and
VINSNS (Pin 31):
VIN Sense Pin. Connects to the VIN Ch1-CLKOUT phase relationship. power supply to provide line feedforward compensation. 3860fc 8 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL DIAGRAM OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS