Datasheet LTC3868-1 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | Low IQ, Dual 2-Phase Synchronous Step-Down Controller |
| Páginas / Página | 38 / 9 — PIN FUNCTIONS (QFN/SSOP). INTVCC (Pin 17/Pin 19):. TG1, TG2 (Pin 24, Pin … |
| Formato / tamaño de archivo | PDF / 475 Kb |
| Idioma del documento | Inglés |
PIN FUNCTIONS (QFN/SSOP). INTVCC (Pin 17/Pin 19):. TG1, TG2 (Pin 24, Pin 13/Pin 26, Pin 15):. PGOOD1 (Pin 25/Pin 27):
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LTC3868-1
PIN FUNCTIONS (QFN/SSOP) INTVCC (Pin 17/Pin 19):
Output of the Internal Linear Low
TG1, TG2 (Pin 24, Pin 13/Pin 26, Pin 15):
High Current Dropout Regulator. The driver and control circuits are Gate Drives for Top N-Channel MOSFETs. These are the powered from this voltage source. Must be decoupled to outputs of fl oating drivers with a voltage swing equal to power ground with a minimum of 4.7μF ceramic or other INTVCC – 0.5V superimposed on the switch node voltage low ESR capacitor. Do not use the INTVCC pin for any SW. other purpose.
PGOOD1 (Pin 25/Pin 27):
Open-Drain Logic Output.
EXTVCC (Pin 18/Pin 20):
External Power Input to an PGOOD1 is pulled to ground when the voltage on the VFB1 Internal LDO Connected to INTVCC. This LDO supplies pin is not within ±10% of its set point. INTVCC power, bypassing the internal LDO powered from
SS1, SS2 (Pin 26, Pin 12/Pin 28, Pin 14):
External Soft- VIN whenever EXTVCC is higher than 4.7V. See EXTVCC Start Input. The LTC3868-1 regulates the V Connection in the Applications Information section. Do FB1,2 voltage to the smaller of 0.8V or the voltage on the SS1,2 pin. An not exceed 14V on this pin. internal 1μA pull-up current source is connected to this
PGND (Pin 19/Pin 21):
Driver Power Ground. Connects to pin. A capacitor to ground at this pin sets the ramp time the sources of bottom (synchronous) N-channel MOSFETs to fi nal regulated output voltage. This pin is also used as and the (–) terminal(s) of CIN. the short-circuit latchoff timer.
VIN (Pin 20/Pin 22):
Main Supply Pin. A bypass capaci-
ITH1, ITH2 (Pin 27, Pin 11/Pin 1, Pin 13):
Error Amplifi er tor should be tied between this pin and the signal ground Outputs and Switching Regulator Compensation Points. pin. Each associated channel’s current comparator trip point
BG1, BG2 (Pin 21, Pin 16/Pin 23, Pin 18):
High Current increases with this control voltage. Gate Drives for Bottom (Synchronous) N-Channel
VFB1, VFB2 (Pin 28, Pin 10/Pin 2, Pin 12):
Receives the MOSFETs. Voltage swing at these pins is from ground remotely sensed feedback voltage for each controller from to INTVCC. an external resistive divider across the output.
BOOST1, BOOST2 (Pin 22, Pin 15/Pin 24, Pin 17):
Boot-
SENSE1+, SENSE2+ (Pin 1, Pin 9/Pin 3, Pin 11):
The (+) strapped Supplies to the Topside Floating Drivers. Capacitors input to the differential current comparators are normally are connected between the BOOST and SW pins and connected to DCR sensing networks or current sensing Schottky diodes are tied between the BOOST and INTVCC resistors. The ITH pin voltage and controlled offsets between pins. Voltage swing at the BOOST pins is from INTVCC to the SENSE– and SENSE+ pins in conjunction with RSENSE (VIN + INTVCC). set the current trip threshold.
SW1, SW2 (Pin 23, Pin 14/Pin 25, Pin 16):
Switch Node Connections to Inductors. 38681fd 9
PIN FUNCTIONS (QFN/SSOP) INTVCC (Pin 17/Pin 19):
Output of the Internal Linear Low
TG1, TG2 (Pin 24, Pin 13/Pin 26, Pin 15):
High Current Dropout Regulator. The driver and control circuits are Gate Drives for Top N-Channel MOSFETs. These are the powered from this voltage source. Must be decoupled to outputs of fl oating drivers with a voltage swing equal to power ground with a minimum of 4.7μF ceramic or other INTVCC – 0.5V superimposed on the switch node voltage low ESR capacitor. Do not use the INTVCC pin for any SW. other purpose.
PGOOD1 (Pin 25/Pin 27):
Open-Drain Logic Output.
EXTVCC (Pin 18/Pin 20):
External Power Input to an PGOOD1 is pulled to ground when the voltage on the VFB1 Internal LDO Connected to INTVCC. This LDO supplies pin is not within ±10% of its set point. INTVCC power, bypassing the internal LDO powered from
SS1, SS2 (Pin 26, Pin 12/Pin 28, Pin 14):
External Soft- VIN whenever EXTVCC is higher than 4.7V. See EXTVCC Start Input. The LTC3868-1 regulates the V Connection in the Applications Information section. Do FB1,2 voltage to the smaller of 0.8V or the voltage on the SS1,2 pin. An not exceed 14V on this pin. internal 1μA pull-up current source is connected to this
PGND (Pin 19/Pin 21):
Driver Power Ground. Connects to pin. A capacitor to ground at this pin sets the ramp time the sources of bottom (synchronous) N-channel MOSFETs to fi nal regulated output voltage. This pin is also used as and the (–) terminal(s) of CIN. the short-circuit latchoff timer.
VIN (Pin 20/Pin 22):
Main Supply Pin. A bypass capaci-
ITH1, ITH2 (Pin 27, Pin 11/Pin 1, Pin 13):
Error Amplifi er tor should be tied between this pin and the signal ground Outputs and Switching Regulator Compensation Points. pin. Each associated channel’s current comparator trip point
BG1, BG2 (Pin 21, Pin 16/Pin 23, Pin 18):
High Current increases with this control voltage. Gate Drives for Bottom (Synchronous) N-Channel
VFB1, VFB2 (Pin 28, Pin 10/Pin 2, Pin 12):
Receives the MOSFETs. Voltage swing at these pins is from ground remotely sensed feedback voltage for each controller from to INTVCC. an external resistive divider across the output.
BOOST1, BOOST2 (Pin 22, Pin 15/Pin 24, Pin 17):
Boot-
SENSE1+, SENSE2+ (Pin 1, Pin 9/Pin 3, Pin 11):
The (+) strapped Supplies to the Topside Floating Drivers. Capacitors input to the differential current comparators are normally are connected between the BOOST and SW pins and connected to DCR sensing networks or current sensing Schottky diodes are tied between the BOOST and INTVCC resistors. The ITH pin voltage and controlled offsets between pins. Voltage swing at the BOOST pins is from INTVCC to the SENSE– and SENSE+ pins in conjunction with RSENSE (VIN + INTVCC). set the current trip threshold.
SW1, SW2 (Pin 23, Pin 14/Pin 25, Pin 16):
Switch Node Connections to Inductors. 38681fd 9