Datasheet LTC3838-1 (Analog Devices) - 4
| Fabricante | Analog Devices |
| Descripción | Dual, Fast, Accurate Step-Down DC/DC Controller with Dual Differential Output Sensing |
| Páginas / Página | 54 / 4 — e lecTrical characTerisTics The. denotes the specifications which apply … |
| Formato / tamaño de archivo | PDF / 890 Kb |
| Idioma del documento | Inglés |
e lecTrical characTerisTics The. denotes the specifications which apply over the specified operating
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LTC3838-1
e lecTrical characTerisTics The
l
denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted (Note 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Start-Up and Shutdown
VRUN1,2 RUN Pin On Threshold VRUN1,2 Rising l 1.1 1.2 1.3 V RUN Pin On Hysteresis VRUN1,2 Falling from On Threshold 100 mV IRUN1,2 RUN Pin Pull-Up Current When Off RUN1,2 = SGND 1.2 µA RUN Pin Pull-Up Current Hysteresis IRUN1,2(HYS) = IRUN1,2(ON) – IRUN1,2(OFF) 5 µA UVLO INTVCC Undervoltage Lockout INTVCC Falling l 3.3 3.7 V INTVCC Rising l 4.2 4.5 V ITRACK/SS1,2 Soft-Start Pull-Up Current 0V < TRACK/SS1,2 < 0.6V 1 µA
Frequency and Clock Synchronization
f Clock Output Frequency RT = 205k 200 kHz (Steady-State Switching Frequency) RT = 80.6k 450 500 550 kHz RT = 18.2k 2000 kHz Channel 2 Phase (Relative to Channel 1) PHASMD = SGND 180 Deg PHASMD = Floating 180 Deg PHASMD = INTVCC 240 Deg CLKOUT Phase (Relative to Channel 1) PHASMD = SGND 60 Deg PHASMD = Floating 90 Deg PHASMD = INTVCC 120 Deg VPLLIN(H) Clock Input High Level Into MODE/PLLIN 2 V VPLLIN(L) Clock Input Low Level Into MODE/PLLIN 0.5 V RMODE/PLLIN MODE/PLLIN Input DC Resistance With Respect to SGND 600 kΩ
Gate Drivers
RTG(UP)1,2 TG Driver Pull-Up On Resistance TG High 2.5 Ω RTG(DOWN)1,2 TG Driver Pull-Down On Resistance TG Low 1.2 Ω RBG(UP)1,2 BG Driver Pull-Up On Resistance BG High 2.5 Ω RBG(DOWN)1,2 BG Driver Pull-Down On Resistance BG Low 0.8 Ω tD(TG/BG)1,2 Top Gate Off to Bottom Gate On Delay Time (Note 6) 20 ns tD(BG/TG)1,2 Bottom Gate Off to Top Gate On Delay Time (Note 6) 15 ns
Internal VCC Regulator
VDRVCC1 Internally Regulated DRVCC1 Voltage 6V < VIN < 38V 5.0 5.3 5.6 V DRVCC1 Load Regulation IDRVCC1 = 0mA to –100mA –1.5 –3 % VEXTVCC EXTVCC Switchover Voltage EXTVCC Rising 4.4 4.6 4.8 V EXTVCC Switchover Hysteresis 200 mV EXTVCC to DRVCC2 Voltage Drop VEXTVCC = 5V, IDRVCC2 = –100mA 200 mV
PGood Output
OV PGOOD Overvoltage Threshold VFB1,2 Rising from Regulated Voltage 5 7.5 10 % UV PGOOD Undervoltage Threshold VFB1,2 Falling from Regulated Voltage –5 –7.5 –10 % PGOOD Threshold Hysteresis VFB1,2 Returning to Regulated Voltage 2.5 % VPGOOD(L)1,2 PGOOD Low Voltage IPGOOD = 2mA 0.1 0.3 V tD(PGOOD)1,2 Delay from VFB Fault (OV/UV) to PGOOD Falling 50 µs Delay from VFB Good (OV/UV Cleared) to PGOOD 20 µs Rising 38381fa 4 For more information www.linear.com/3838-1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
e lecTrical characTerisTics The
l
denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted (Note 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Start-Up and Shutdown
VRUN1,2 RUN Pin On Threshold VRUN1,2 Rising l 1.1 1.2 1.3 V RUN Pin On Hysteresis VRUN1,2 Falling from On Threshold 100 mV IRUN1,2 RUN Pin Pull-Up Current When Off RUN1,2 = SGND 1.2 µA RUN Pin Pull-Up Current Hysteresis IRUN1,2(HYS) = IRUN1,2(ON) – IRUN1,2(OFF) 5 µA UVLO INTVCC Undervoltage Lockout INTVCC Falling l 3.3 3.7 V INTVCC Rising l 4.2 4.5 V ITRACK/SS1,2 Soft-Start Pull-Up Current 0V < TRACK/SS1,2 < 0.6V 1 µA
Frequency and Clock Synchronization
f Clock Output Frequency RT = 205k 200 kHz (Steady-State Switching Frequency) RT = 80.6k 450 500 550 kHz RT = 18.2k 2000 kHz Channel 2 Phase (Relative to Channel 1) PHASMD = SGND 180 Deg PHASMD = Floating 180 Deg PHASMD = INTVCC 240 Deg CLKOUT Phase (Relative to Channel 1) PHASMD = SGND 60 Deg PHASMD = Floating 90 Deg PHASMD = INTVCC 120 Deg VPLLIN(H) Clock Input High Level Into MODE/PLLIN 2 V VPLLIN(L) Clock Input Low Level Into MODE/PLLIN 0.5 V RMODE/PLLIN MODE/PLLIN Input DC Resistance With Respect to SGND 600 kΩ
Gate Drivers
RTG(UP)1,2 TG Driver Pull-Up On Resistance TG High 2.5 Ω RTG(DOWN)1,2 TG Driver Pull-Down On Resistance TG Low 1.2 Ω RBG(UP)1,2 BG Driver Pull-Up On Resistance BG High 2.5 Ω RBG(DOWN)1,2 BG Driver Pull-Down On Resistance BG Low 0.8 Ω tD(TG/BG)1,2 Top Gate Off to Bottom Gate On Delay Time (Note 6) 20 ns tD(BG/TG)1,2 Bottom Gate Off to Top Gate On Delay Time (Note 6) 15 ns
Internal VCC Regulator
VDRVCC1 Internally Regulated DRVCC1 Voltage 6V < VIN < 38V 5.0 5.3 5.6 V DRVCC1 Load Regulation IDRVCC1 = 0mA to –100mA –1.5 –3 % VEXTVCC EXTVCC Switchover Voltage EXTVCC Rising 4.4 4.6 4.8 V EXTVCC Switchover Hysteresis 200 mV EXTVCC to DRVCC2 Voltage Drop VEXTVCC = 5V, IDRVCC2 = –100mA 200 mV
PGood Output
OV PGOOD Overvoltage Threshold VFB1,2 Rising from Regulated Voltage 5 7.5 10 % UV PGOOD Undervoltage Threshold VFB1,2 Falling from Regulated Voltage –5 –7.5 –10 % PGOOD Threshold Hysteresis VFB1,2 Returning to Regulated Voltage 2.5 % VPGOOD(L)1,2 PGOOD Low Voltage IPGOOD = 2mA 0.1 0.3 V tD(PGOOD)1,2 Delay from VFB Fault (OV/UV) to PGOOD Falling 50 µs Delay from VFB Good (OV/UV Cleared) to PGOOD 20 µs Rising 38381fa 4 For more information www.linear.com/3838-1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts