Datasheet ADP3050 (Analog Devices) - 10

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ADP3050 Data Sheet THEORY OF OPERATION
The ADP3050 is a fixed frequency, current mode buck regulator.
3.3V VOUT
Current mode systems provide excellent transient response, and
+ C4 L1
are much easier to compensate than voltage mode systems (refer to
100µF 33µH D2
Figure 1). At the beginning of each clock cycle, the oscillator
1N4148 D1 1 SWITCH IN 8
sets the latch, turning on the power switch. The signal at the
C3 1N5818 220nF
noninverting input of the comparator is a replica of the switch
2 BOOST GND 7
current (summed with the oscillator ramp). When this signal
3 BIAS SD 6
reaches the appropriate level set by the output of the error amplifier, the comparator resets the latch and turns off the power switch. In
4 FB COMP 5 R1
this manner, the error amplifier sets the correct current trip
U1 4kΩ ADP3050-3.3 C2
level to keep the output in regulation. If the error amplifier
1nF
output increases, more current is delivered to the output; if it
12V VIN
decreases, less current is delivered to the output.
+ C1 22µF
024 The current sense amplifier provides a signal proportional to 00125- switch current to both the comparator and to a cycle-by-cycle Figure 24. Typical Application Circuit current limit. If the current limit is exceeded, the latch is reset,
SETTING THE OUTPUT VOLTAGE
turning the switch off until the beginning of the next clock The output of the adjustable version (ADP3050AR and cycle. The ADP3050 has a foldback current limit that reduces ADP3050ARZ) can be set to any voltage between 1.25 V and 12 V the switching frequency under fault conditions to reduce stress by connecting a resistor divider to the FB pin as shown in to the IC and to the external components. Figure 25. Most of the control circuitry is biased from the 2.5 V internal  V  regulator. When the BIAS pin is left open, or when the voltage R2 = R1 ×  OUT −  1 (1) at this pin is less than 2.7 V, all of the operating current for the  2 . 1  ADP3050 is drawn from the input supply. When the BIAS pin is
L1 22µH
above 2.7 V, the majority of the operating current is drawn from
2.5V V
this pin (usually tied to the low voltage output of the regulator)
OUT D1 + C4
instead of from the higher voltage input supply. This can provide
2×22µF 1N5817 CERAMIC
substantial efficiency improvements at light load conditions,
1 SWITCH IN 8 C3
especially for systems where the input voltage is much higher
0.22µF 2 BOOST GND 7
than the output voltage.
C R2 F 3 BIAS SD 6
The ADP3050 uses a special drive stage allowing the power
21.5kΩ
switch to saturate. An external diode and capacitor provide a
4 FB COMP 5 D2 R1 RC
boosted voltage to the drive stage that is higher than the input
1N4148 20kΩ U1 7.5kΩ C
supply voltage. Overall efficiency is dramatically improved by
ADP3050 C 4.7nF
using this type of saturating drive stage.
5V VIN C1
Pulling the SD pin below 0.4 V puts the device in a low power
+ C2 2×10µF 0.01µF
mode, shutting off all internal circuitry and reducing the supply
CERAMIC
025
GND
current to under 20 μA. 00125- Figure 25. Adjustable Output Application Circuit Rev. C | Page 10 of 20 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Setting the Output Voltage Applications Information ADIsimPower Design Tool Inductor Selection Continuous Mode Discontinuous Mode Inductor Core Types and Materials Choosing an Inductor Output Capacitor Selection Choosing an Output Capacitor Catch Diode Selection Choosing a Catch Diode Input Capacitor Selection Discontinous Mode Ringing Setting the Output Voltage Frequency Compensation Current Limit/Frequency Foldback Bias Pin Connection Boosted Drive Stage Start-Up/Minimum Input Voltage Thermal Considerations Board Layout Guidelines Typical Applications 5 V to 3.3 V Buck (Step-Down) Regulator Inverting (Buck Boost) Regulator Dual Output SEPIC Regulator Outline Dimensions Ordering Guide