Datasheet LTC1875 (Analog Devices) - 8

LTC1875
U OPERATIO (Refer to Block Diagram) Main Control Loop
the ITH voltage drops below approximately 0.45V, the BURST comparator trips, turning off both power MOSFETs. The LTC1875 uses a constant frequency, current mode The I step-down architecture. Both the top MOSFET and syn- TH pin is then disconnected from the output of the EA amplifier and held 0.65V above ground. chronous bottom MOSFET switches are internal. During normal operation, the internal top power MOSFET is In sleep mode, both power MOSFETs are held off and the turned on each cycle when the oscillator sets the RS latch, internal circuitry is partially turned off, reducing the quies- and turned off when the current comparator, ICOMP, resets cent current to 15µA. The load current is now being the RS latch. The peak inductor current at which ICOMP supplied from the output capacitor. When the output turns the top MOSFET off is controlled by the voltage on voltage drops, the ITH pin reconnects to the output of the the ITH pin, which is the output of error amplifier EA. When EA amplifier and the top MOSFET is again turned on and the load current increases, it causes a slight decrease in this process repeats. the feedback voltage, VFB, relative to the 0.8V internal reference, which, in turn, causes the I
Soft-Start/Run Function
TH voltage to in- crease until the average inductor current matches the new The RUN/SS pin provides a soft-start function and a load current. While the top MOSFET is off, the bottom means to shut down the LTC1875. Soft-start reduces the MOSFET is turned on until either the inductor current input current surge by gradually increasing the regulator’s starts to reverse direction or the next clock cycle begins. maximum output current. This pin can also be used for Comparator OVDET guards against transient overshoots power supply sequencing. > 7.5% by turning the main switch off and keeping it off Pulling the RUN/SS pin below 0.7V shuts down the until the fault is removed. LTC1875, which then draws < 1µA current from the sup- ply. This pin can be driven directly from logic circuits as
Burst Mode Operation
shown in Figure 1. It is recommended that this pin is driven The LTC1875 is capable of Burst Mode operation in which to VIN during normal operation. Note that there is no the internal power MOSFETs operate intermittently based current flowing out of this pin. Soft-start action is accom- on load demand. To enable Burst Mode operation, simply plished by connecting an external RC network to the RUN/ tie the SYNC/MODE pin to SVIN or connect it to a logic high SS pin as shown in Figure 1. The LTC1875 actively pulls (VSYNC/MODE > 1.5V). To disable Burst Mode operation the RUN/SS pin to ground under low input supply voltage and enable PWM pulse skipping mode, connect the SYNC/ conditions. MODE pin to SGND. In this mode, the efficiency is lower at light loads but becomes comparable to Burst Mode opera- V tion when the output load exceeds 100mA. The advantage IN of pulse skipping mode is lower output ripple. 3.3V OR 5V D1* R 0.32V SS When the converter is in Burst Mode operation, the peak RUN/SS current of the inductor is set to approximately 400mA, CSS even though the voltage at the I *ZETEX BAT54 TH pin indicates a lower 1875 F01 value. The voltage at the ITH pin drops when the inductor’s average current is greater than the load requirement. As
Figure 1. RUN/SS Pin Interfacing
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