Datasheet LT1940, LT1940L (Analog Devices) - 6

FabricanteAnalog Devices
DescripciónDual Monolithic 1.4A, 1.1MHz Step-Down Switching Regulator
Páginas / Página20 / 6 — BLOCK DIAGRA
Formato / tamaño de archivoPDF / 288 Kb
Idioma del documentoInglés

BLOCK DIAGRA

BLOCK DIAGRA

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LT1940/LT1940L
W BLOCK DIAGRA
VIN 2µA RUN/SS2 CLK1 INT REG MASTER AND REF OSC CLK2 2µA VIN RUN/SS1 IN CIN 0.75V ∑ SLOPE R BOOST D2 S Q C1 SLAVE C3 OSC CLK SW L1 OUT + C1 D1 – ERROR 0.5V FB AMP – R1 VC R2 + RC – 1.25V CF C RUN/SS C + I 125mV LIMIT CLAMP PG + GND – 1940 F02
Figure 2. Block Diagram of the LT1940 with Associated External Components (One of Two Switching Regulators Shown)
The LT1940 is a dual, constant frequency, current mode these pins. If either RUN/SS pin exceeds 0.6V, the internal buck regulator with internal 2A power switches. The two bias circuits turn on, including the internal regulator, regulators share common circuitry including input source, 1.25V reference and 1.1MHz master oscillator. In this voltage reference and oscillator, but are otherwise inde- state, the LT1940 draws 3.5mA from VIN, whether one or pendent. This section describes the operation of the both RUN/SS pins are high. Neither switching regulator LT1940; refer to the Block Diagram. will begin to operate until its RUN/SS pin reaches ~0.8V. The master oscillator generates two clock signals of If the RUN/SS (run/soft-start) pins are both tied to ground, opposite phase. the LT1940 is shut down and draws 30µA from the input source tied to VIN. Internal 2µA current sources charge The two switchers are current mode step-down regula- external soft-start capacitors, generating voltage ramps at tors. This means that instead of directly modulating the 1940fa 6