Datasheet LTC3406-1.2 (Analog Devices) - 10

LTC3406-1.2
U U W U APPLICATIO S I FOR ATIO
The regulator loop then acts to return VOUT to its steady-
Design Example
state value. During this recovery time VOUT can be moni- As a design example, assume the LTC3406-1.2 is used in tored for overshoot or ringing that would indicate a stability a single lithium-ion battery-powered cellular phone problem. For a detailed explanation of switching control application. The V loop theory, see Application Note 76. IN will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement A second, more severe transient is caused by switching in is a maximum of 0.6A but most of the time it will be in loads with large (>1µF) supply bypass capacitors. The standby mode, requiring only 2mA. Efficiency at both low discharged bypass capacitors are effectively put in parallel and high load currents is important. With this informa- with COUT, causing a rapid drop in VOUT. No regulator can tion we can calculate L using equation (1), deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only 1 ⎛ 1. V 2 ⎞ L = 1. V 2 1 (3) solution is to limit the rise time of the switch drive so that (f)(∆I ) − ⎝⎜ V L IN ⎠ ⎟ the load rise time is limited to approximately (25 • CLOAD). Thus, a 10µF capacitor charging to 3.3V would require a Substituting VIN = 4.2V, ∆IL = 240mA and f = 1.5MHz in 250µs rise time, limiting the charging current to about equation (3) gives: 130mA. 1. V 2 ⎛ 1. V 2 ⎞ L = 1− 2 3 . 8 H
PC Board Layout Checklist
1. MHz 5 ( mA 240 )⎝⎜ 4. V 2 ⎠⎟ = µ When laying out the printed circuit board, the following A 2.2µH inductor works well for this application. For best checklist should be used to ensure proper operation of the efficiency choose a 720mA or greater inductor with less LTC3406-1.2. These items are also illustrated graphically than 0.2Ω series resistance. in Figures 3 and 4. Check the following in your layout: CIN will require an RMS current rating of at least 0.3A ≅ 1. The power traces, consisting of the GND trace, the SW ILOAD(MAX)/2 at temperature and COUT will require an ESR trace and the VIN trace should be kept short, direct and of less than 0.25Ω. In most cases, a ceramic capacitor will wide. satisfy this requirement. 2. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the internal power MOSFETs. 3. Keep the (–) plates of CIN and COUT as close as possible. VIA TO VOUT VIN VIA TO VIN 1 RUN LTC3406-1.2 2 PIN 1 5 GND – VOUT V V LTC3406-1.2 OUT COUT OUT 3 4 + SW VIN L1 SW L1 CIN VIN COUT CIN 340612 F03 GND BOLD LINES INDICATE HIGH CURRENT PATHS 340612 F04
Figure 3. LTC3406-1.2 Layout Diagram Figure 4. LTC3406-1.2 Suggested Layout
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