Datasheet LTC3415 (Analog Devices) - 7

LTC3415
PIN FUNCTIONS SGND (Pin 2):
Signal Ground. Return ground path for
BSEL (Pin 21):
Margining Bit Select Pin. Tying BSEL low all analog and low power circuitry. Single connection to selects ±5%, tying it high selects ±10%. Tying it to VIN/2 PGND on system board. selects ±15%.
PLLLPF (Pin 3):
Phase-Locked-Loop Lowpass Filter. The
PGOOD (Pin 22):
Output Power GOOD with Open-Drain PLL’s lowpass fi lter is tied to this pin. In spread spectrum Logic. PGOOD is pulled to ground when the voltage on mode, placing a capacitor here to SGND controls the slew the VFB pin is not within ±10% of its set point. Disabled rate from one frequency to the next. Alternatively, fl oating during margining and during slave mode operation (VFB this pin allows normal running frequency at 1.5MHz, tying tied to VIN). this pin to SVIN forces the part to run at 1.33 times its normal
V
frequency (2MHz), tying it to ground forces the frequency
FB (Pin 29):
Input to the error amplifi er that compares the feedback voltage to the internal 0.6V reference voltage. to run at 0.67 times its normal frequency (1MHz). This pin is normally connected to a resistive divider from
PVIN (Pins 4, 5, 27, 28, 35, 36):
Power VIN. Input voltage the output voltage. In PolyPhase operation, tying VFB to to the on chip power MOSFETs. Must be closely decoupled SVIN disables its own internal error amplifi er and connects to PGND. the master’s ITH voltage to its current comparator.
SW (Pins 6, 7, 8, 9, 23, 24, 25, 26):
Switch Node Con-
TRACK (Pin 30):
Track Input Pin. This allows the user to nection to the Inductor. This pin swings from PVIN to control the rise time of the output. Putting a voltage below PGND. 0.57V on this pin bypasses the reference input into the er- ror amplifi er and servos the V
MODE (Pin 10):
Mode Select Input. Tying this pin high FB pin to the TRACK voltage. Above 0.57V, the tracking function stops and the internal enables Burst Mode operation. Tying this pin low enables reference again controls the error amplifi er. During shut- force continuous operation. Tying it to VIN/2 enables pulse- down, if TRACK is not tied to SV skipping operation. IN, then TRACK’s voltage needs to be below 0.18V before the chip shuts down even
CLKIN (Pin 11):
External Synchronization Input to Phase though RUN is already low. Do not fl oat this pin. Detector. This pin is internally terminated to SGND with a
I
50k resistor. The phase-locked-loop will force the internal
TH (Pin 32):
Error Amplifi er Output and Switching Regulator Compensation Point. The current comparator’s top power PMOS turn on to be synchronized with the threshold increases with this control voltage. The normal rising edge of the CLKIN signal. Connect this pin to SVIN voltage range of this pin is from 0V to 1.5V. It’s also the to enable spread spectrum modulation. During external positive input to the internal I synchronization, make sure the PLLLPF pin is not tied to TH differential amplifi er. Tying I V TH to SVIN enables the internal compensation. IN or GND.
I PHMODE THM (Pin 33):
Negative Input to the Internal ITH Differential
(Pin 12):
Phase Selector Input. This pin deter- Amplifi er. Tie this pin to SGND for single phase operation. mines the phase relationship between the internal oscil- For PolyPhase, tie the master’s I lator and CLKOUT. Tie it high for 2-phase operation, tie it THM to SGND while con- necting all of the I low for 3-phase operation, and tie it to V THM pins together. IN/2 for 4-phase operation.
SVIN (Pin 34):
Signal Input Voltage. Connect this pin to PV
PGND (Pins 13-19):
Power Ground. Return path of internal IN through a 1Ω and 0.1μF lowpass fi lter. N-channel power MOSFETs. Connect this pin with the (–)
RUN (Pin 37):
Run Control Input. Tying this pin above terminals of CIN and COUT. 1.5V turns on the part.
MGN (Pin 20):
Margining Pin. Tying this pin to a voltage
CLKOUT (Pin 38):
Output Clock Signal for PolyPhase between 0.5V and SVIN – 0.5V disables the margining Operation. The phase of CLKOUT is determined by the function and allows normal operation. Tying it high enables state of the PHMODE pin. positive margining (5, 10, or 15%). Tying it low enables
Exposed Pad (Pin 39):
Power Ground. Must be connected negative margining (–5, –10, or –15%). to electrical ground on PCB. 3415fa 7