Datasheet LTC3541-3 (Analog Devices) - 10

LTC3541-3
OPERATION
The LTC3541-3 contains a high efficiency synchronous
Buck Regulator Control Loop
buck converter, a very low dropout regulator (VLDO) and The LTC3541-3 internal buck regulator uses a constant a linear regulator. It can be used to provide up to two frequency, current mode, step-down architecture. Both the output voltages from a single input voltage making the main (top, P-channel MOSFET) and synchronous (bottom, LTC3541-3 ideal for applications with limited board space. N-channel MOSFET) switches are internal. During normal The combination and configuration of these major blocks operation, the internal main switch is turned on at the be- within the LTC3541-3 is determined by way of the control ginning of each clock cycle provided the internal feedback pins ENBUCK and ENVLDO as defined in Table 1. voltage to the buck is less than the reference voltage. The With the ENBUCK pin driven to a logic high and ENVLDO current into the inductor provided to the load increases driven to a logic low, the LTC3541-3 enables the buck until the current limit is reached. Once the current limit is converter to efficiently reduce the voltage provided at the reached the main switch turns off and the energy stored VIN input pin to an output voltage of 1.8V as determined by in the inductor flows through the bottom synchronous an internal feedback resistor network. The buck regulator switch into the load until the next clock cycle. can be configured for Pulse-Skip or Burst Mode opera- The peak inductor current is determined by comparing the tion by driving the MODE pin to a logic high or logic low buck feedback signal to an internal 0.8V reference. When respectively. The buck regulator is capable of providing the load current increases, the output of the buck and a maximum output current of 500mA, which must be hence the buck feedback signal decrease. This decrease taken into consideration when using the buck regulator causes the peak inductor current to increase until the aver- to provide the power for both the VLDO regulator and for age inductor current matches the load current. While the external loads. main switch is off, the synchronous switch is turned on With the ENBUCK pin driven to a logic low and ENVLDO until either the inductor current starts to reverse direction driven to a logic high, the LTC3541-3 enables the linear or the beginning of a new clock cycle. regulator, providing a low noise regulated output voltage of When the MODE pin is driven to a logic low, the LTC3541-3 1.575V at the LVOUT pin while drawing minimal quiescent buck regulator operates in Burst Mode operation for high current from the VIN input pin. This feature allows output efficiency. In this mode, the main switch operates based voltage LVOUT to be brought into regulation without the upon load demand. In Burst Mode operation the peak presence of the LVIN voltage. inductor current is set to a fixed value, where each burst With the ENBUCK and ENVLDO pins both driven to a logic event can last from a few clock cycles at light loads to high, the LTC3541-3 enables the high efficiency buck con- nearly continuous cycling at moderate loads. Between verter and VLDO, providing dual output operation from a burst events the main switch and any unneeded circuitry single input voltage. When configured in this manner, the are turned off, reducing the quiescent current. In this sleep LTC3541-3’s auto start-up sequencing feature will initially state, the load is being supplied solely from the output bring the VLDO/linear regulator output (1.575V) into regula- capacitor. As the output voltage droops, an internal error tion in a controlled manner using the linear regulator prior amplifier’s output rises until a wake threshold is reached to enabling the buck output (1.8V) without the need for causing the main switch to again turn on. This process external pin control. The LTC3541-3 automatically transi- repeats at a rate that is dependant upon the load current tions the VLDO/linear regulator output (1.575V) from the demand. linear regulator to the VLDO regulator within 20ms of buck soft-start initiation. A detailed discussion of the transitions between the VLDO regulator and linear regulator can be found in the VLDO/Linear Regulator Loop section. 35413fd 10 For more information www.linear.com/LTC3541-3 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Related Parts