Datasheet LTC3542 (Analog Devices) - 10

LTC3542
APPLICATIONS INFORMATION Output Voltage Programming
Although all dissipative elements in the circuit produce losses, three main sources usually account for most of The output voltage is set by a resistive divider according the losses in LTC3542 circuits: 1) V to the following formula: IN quiescent current, 2) I2R loss and 3) switching loss. VIN quiescent current ⎛ R2⎞ loss dominates the power loss at very low load currents, V 0 6 . V OUT = + 1 whereas the other two dominate at medium to high load ⎝⎜ R1⎠⎟ currents. In a typical effi ciency plot, the effi ciency curve To improve the frequency response, a feed-forward capaci- at very low load currents can be misleading since the tor, C actual power loss is of no consequence as illustrated in F, may also be used. Great care should be taken to route the V Figure 2. FB line away from noise sources, such as the inductor or the SW line. 1) The VIN quiescent current is the DC supply current given in the Electrical Characteristics which excludes MOSFET
Mode Selection and Frequency Synchronization
charging current. VIN current results in a small (<0.1%) The MODE/SYNC pin is a multipurpose pin that provides loss that increases with VIN, even at no load. mode selection and frequency synchronization. Connect- 2) I2R losses are calculated from the DC resistances of ing this pin to GND enables Burst Mode operation, which the internal switches, R provides the best low current effi ciency at the cost of a SW, and external inductor, RL. In continuous mode, the average output current fl ows through higher output voltage ripple. Connecting this pin to VIN inductor L, but is “chopped” between the internal top and selects pulse skip mode operation, which provides the bottom switches. Thus, the series resistance looking into lowest output ripple at the cost of low current effi ciency. the SW pin is a function of both top and bottom MOSFET The LTC3542 can also be synchronized to an external clock R signal with range from 1MHz to 3MHz by the MODE/SYNC DS(ON) and the duty cycle (D) as follows: pin. During synchronization, the mode is set to pulse skip RSW = (RDS(ON)TOP)(D) + (RDS(ON)BOT)(1 – D) and the top switch turn-on is synchronized to the falling The RDS(ON) for both the top and bottom MOSFETs can edge of the external clock. be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses:
Effi ciency Considerations
I2R losses = I 2(R The effi ciency of a switching regulator is equal to the output OUT SW + RL) power divided by the input power times 100%. It is often 1000 V useful to analyze individual losses to determine what is IN = 3.6V Burst Mode OPERATION limiting the effi ciency and which change would produce 100 the most improvement. Effi ciency can be expressed as: Effi ciency = 100% – (L1 + L2 + L3 + ...) 10 where L1, L2, etc. are the individual losses as a percent- age of input power. POWER LOSS (mW) 1 VOUT = 2.5V VOUT = 1.8V VOUT = 1.2V 0.1 0.1 1 10 100 1000 OUTPUT CURRENT (mA) 3542 F02
Figure 2. Power Loss vs Load Current
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