Datasheet LT3681 (Analog Devices) - 8

FabricanteAnalog Devices
Descripción36V, 2A, 2.8MHz Step-Down Switching Regulator with Integrated Power Schottky Diode
Páginas / Página24 / 8 — BLOCK DIAGRA. OPERATION
Formato / tamaño de archivoPDF / 381 Kb
Idioma del documentoInglés

BLOCK DIAGRA. OPERATION

BLOCK DIAGRA OPERATION

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LT3681
W BLOCK DIAGRA
VIN VIN 13 C1 BIAS – 2 INTERNAL 1.265V REF + BD 10 RUN/SS 14 SLOPE COMP 5 SWITCH BOOST LATCH 11 C3 R RT OSCILLATOR Q 6 300kHz–2.8MHz S L1 SW R V 12 OUT T DISABLE C2 DC SOFT-START BurstMode 9 DETECT DC 16 PG 1 DA ERROR AMP VC CLAMP 8 + 1.12V + VC 5 – – CC CF RC GND GND GND FB 4 7 15 3 R2 R1 3681 BD
OPERATION
The LT3681 is a constant frequency, current mode step- The switch driver operates from either the input or from down regulator. An oscillator, with frequency set by RT, the BOOST pin. An external capacitor is used to generate sets an RS fl ip-fl op, turning on the internal power switch. a voltage at the BOOST pin that is higher than the input An amplifi er and comparator monitor the current fl owing supply. This allows the driver to fully saturate the internal between the VIN and SW pins, turning the switch off when bipolar NPN power switch for effi cient operation. this current reaches a level determined by the voltage at To further optimize effi ciency, the LT3681 automatically VC. An error amplifi er measures the output voltage through switches to Burst Mode operation in light load situations. an external resistor divider tied to the FB pin and servos Between bursts, all circuitry associated with controlling the VC pin. If the error amplifi er’s output increases, more the output switch is shut down reducing the input supply current is delivered to the output; if it decreases, less cur- current to 55µA in a typical application. rent is delivered. An active clamp on the VC pin provides current limit. The V The oscillator reduces the LT3681’s operating frequency C pin is also clamped to the voltage on the RUN/SS pin; soft-start is implemented by generating a when the voltage at the FB pin is low. This frequency voltage ramp at the RUN/SS pin using an external resistor foldback helps to control the output current during startup and capacitor. and overload. An internal regulator provides power to the control cir- The LT3681 contains a power good comparator which trips cuitry. The bias regulator normally draws power from the when the FB pin is at 91% of its regulated value. The PG V output is an open-collector transistor that is off when the IN pin, but if the BIAS pin is connected to an external voltage higher than 3V bias power will be drawn from the output is in regulation, allowing an external resistor to pull external source (typically the regulated output voltage). the PG pin high. Power good is valid when the LT3681 is enabled and V This improves effi ciency. The RUN/SS pin is used to place IN is above 3.6V. the LT3681 in shutdown, disconnecting the output and The LT3681 integrates a high quality, 36V, 2A power reducing the input current to less than 1µA. Schottky diode to reduce the overall solution size. 3681f 8