Datasheet LTC3672B-1 (Analog Devices) - 7

LTC3672B-1
OPERATION INTRODUCTION
on. Energy stored in the inductor discharges into the load through this NMOS. The NMOS turns off at the end of the The LTC3672B-1 combines a synchronous buck converter 2.25MHz cycle, or sooner, if the current through it drops with two low dropout linear DC regulators (LDOs) to to zero before the end of the cycle. provide three low voltage outputs from a higher volt- age input source. All outputs are enabled and disabled Through these mechanisms, the error amplifi er adjusts the together through the ENALL pin. The output regulation peak inductor current to deliver the required output power voltages are set during manufacturing to 1.8V nominal to regulate the output voltage as sensed by the BUCKOUT for the buck, 1.2V nominal for LDO1, and 2.8V nominal pin. All necessary control-loop compensation is internal to for LDO2. LDO1 may be powered off of the buck output the step-down switching regulator, requiring only a single for higher overall effi ciency. ceramic output capacitor for stability. For versions of the IC with different output regulation
Light Load/No-Load Cycle-Skipping
voltages, consult the LTC factory. At light loads, the inductor current may reach zero before the end of the oscillator cycle, which will turn off the NMOS
SYNCHRONOUS BUCK REGULATOR
synchronous rectifi er. In this case, the SW pin goes high The synchronous buck uses a constant-frequency current impedance and will show damped “ringing”. This is known mode architecture, switching at 2.25MHz down to very light as discontinuous operation, and is normal behavior for a loads, and supports no-load operation by skipping cycles. switching regulator. At very light load and no-load condi- When the input voltage drops very close to or falls below tions, the buck will automatically skip cycles as needed the target output voltage, the buck supports 100% duty to maintain output regulation. cycle operation (low dropout mode). Soft-start circuitry limits inrush current when powering on. Output current is
Soft-Start
limited in the event of an output short-circuit. The switch Soft-start in the buck regulator is accomplished by gradually node is slew-rate limited to reduce EMI radiation. The increasing the maximum allowed peak inductor current buck regulation control-loop compensation is internal to over a 200μs period. This allows the output to rise slowly, the IC, and requires no external components. controlling the inrush current required to charge up the output capacitor. A soft-start cycle occurs whenever the
Main Control Loop
LTC3672B-1 is enabled, or after a fault condition has oc- An error amplifi er monitors the difference between an curred (thermal shutdown or UVLO). internal reference voltage and the voltage on the BUCKOUT pin. When the BUCKOUT voltage is below the reference,
Switch Slew-Rate Control
the error amplifi er output voltage increases. When the The buck regulator contains new patent pending circuitry BUCKOUT voltage exceeds the reference, the error ampli- to limit the slew rate of the switch node (SW pin). This fi er output voltage decreases. new circuitry is designed to transition the switch node The error amplifi er output controls the peak inductor current over a period of a couple nanoseconds, signifi cantly through the following mechanism: Paced by a free-running reducing radiated EMI and conducted supply noise while 2.25MHz oscillator, the main P-channel MOSFET switch is maintaining high effi ciency. turned on at the start of the oscillator cycle. Current fl ows from the VIN supply through this PMOS switch, through
LOW VIN SUPPLY UNDERVOLTAGE LOCKOUT
the inductor via the SW pin, and into the output capacitor and load. When the current reaches the level programmed An undervoltage lockout (UVLO) circuit shuts down the by the output of the error amplifi er, the PMOS is shut off, LTC3672B-1 when VIN drops below about 1.7V. and the N-channel MOSFET synchronous rectifi er turns 3672B1f 7