Datasheet LT3500 (Analog Devices) - 10

LT3500
OPERATION
The LT3500 is a constant frequency, current mode buck During power up, the POR signal sets the soft-start latch, converter with an internal 2.3A switch plus a linear regula- which discharges the SS pin to ensure proper start-up tor with 13mA output capability. Control of both outputs operation. When the SS pin voltage drops below 100mV, is achieved with a common SHDN pin, internal regulator, the VC pin is driven low disabling switching and the soft- oscillator, undervoltage detect, soft-start, thermal shut- start latch is reset. Once the latch is reset the soft-start down and power-on reset. capacitor starts to charge with a typical value of 2.75μA. If the SHDN pin is taken below its 0.8V threshold, the As the voltage rises above 100mV on the SS pin, the VC LT3500 will be placed in a low quiescent current mode. pin will be driven high by the error amplifi er. When the In this mode the LT3500 typically draws 12μA from the voltage on the VC pin exceeds 0.8V, the clock set-pulse sets VIN pin. the driver fl ip-fl op which turns on the internal power NPN When the SHDN pin is fl oated or driven above 0.76V, the switch. This causes current from VIN, through the NPN internal bias circuits turn on generating an internal regu- switch, inductor and internal sense resistor, to increase. lated voltage, 0.8(V When the voltage drop across the internal sense resistor FB) and 1V(RT/SYNC) references, and a POR signal which sets the soft-start latch. exceeds a predetermined level set by the voltage on the VC pin, the fl ip-fl op is reset and the internal NPN switch As the RT/SYNC pin reaches its 1V regulation point, the is turned off. Once the switch is turned off the inductor internal oscillator will start generating a clock signal at a will drive the voltage at the SW pin low until the external frequency determined by the resistor from the RT/SYNC Schottky diode starts to conduct, decreasing the current pin to ground. Alternatively, if a synchronization signal is in the inductor. The cycle is repeated with the start of each detected by the LT3500 at the RT/SYNC pin, a clock signal clock cycle. However, if the internal sense resistor voltage will be generated at the incoming frequency on the rising exceeds the predetermined level at the start of a clock cycle, edge of the synchronization pulse. In addition, the internal the fl ip-fl op will not be set resulting in a further decrease in slope compensation will be automatically adjusted to pre- inductor current. Since the output current is controlled by vent subharmonic oscillation during synchronization. the VC voltage, output regulation is achieved by the error The LT3500 is a constant frequency, current mode step- amplifi er continually adjusting the VC pin voltage. down converter. Current mode regulators are controlled The error amplifi er is a transconductance amplifi er that by an internal clock and two feedback loops that control compares the FB voltage to either the SS pin voltage minus the duty cycle of the power switch. In addition to the 100mV or an internally regulated 800mV, whichever is normal error amplifi er, there is a current sense amplifi er lowest. Compensation of the loop is easily achieved with that monitors switch current on a cycle-by-cycle basis. a simple capacitor or series resistor/capacitor from the This technique means that the error amplifi er commands VC pin to ground. current to be delivered to the output rather than voltage. Since the SS pin is driven by a constant current source, a A voltage fed system will have low phase shift up to the single capacitor on the soft-start pin will generate controlled resonant frequency of the inductor and output capacitor, linear ramp on the output voltage. then an abrupt 180° shift will occur. The current fed system If the current demanded by the output exceeds the maxi- will have 90° phase shift at a much lower frequency, but mum current dictated by the V will not have the additional 90° shift until well beyond C pin clamp, the SS pin will be discharged, lowering the regulation point until the the LC resonant frequency. This makes it much easier to output voltage can be supported by the maximum current. frequency compensate the feedback loop and also gives When overload is removed, the output will soft-start from much quicker transient response. the overload regulation point. 3500fc 10