Datasheet LTC3672B-2 (Analog Devices) - 7

LTC3672B-2
OPERATION INTRODUCTION
turned on at the start of the oscillator cycle. Current fl ows from the V The LTC3672B-2 combines a synchronous buck converter IN supply through this PMOS switch, through the inductor via the SW pin, and into the output capacitor with two low dropout linear DC regulators (LDOs) to and load. When the current reaches the level programmed provide three low voltage outputs from a higher voltage by the output of the error amplifi er, the PMOS is shut off, input source. All outputs are enabled and disabled together and the N-channel MOSFET synchronous rectifi er turns through the ENALL pin. The output regulation voltages are on. Energy stored in the inductor discharges into the load set during manufacturing to 1.2V nominal for the buck, through this NMOS. The NMOS turns off at the end of the 2.8V nominal for LDO1, and 1.8V nominal for LDO2. 2.25MHz cycle, or sooner, if the current through it drops For versions of the IC with different output regulation to zero before the end of the cycle. voltages, consult the LTC factory. Through these mechanisms, the error amplifi er adjusts the peak inductor current to deliver the required output power
SYNCHRONOUS BUCK REGULATOR
to regulate the output voltage as sensed by the BUCKOUT The synchronous buck uses a constant-frequency current pin. All necessary control-loop compensation is internal to mode architecture, switching at 2.25MHz down to very light the step-down switching regulator, requiring only a single loads, and supports no-load operation by skipping cycles. ceramic output capacitor for stability. When the input voltage drops very close to or falls below the target output voltage, the buck supports 100% duty
Light Load/No-Load Cycle-Skipping
cycle operation (low dropout mode). Soft-start circuitry At light loads, the inductor current may reach zero before limits inrush current when powering on. Output current is the end of the oscillator cycle, which will turn off the NMOS limited in the event of an output short-circuit. The switch synchronous rectifi er. In this case, the SW pin goes high node is slew-rate limited to reduce EMI radiation. The impedance and will show damped “ringing”. This is known buck regulation control-loop compensation is internal to as discontinuous operation, and is normal behavior for a the IC, and requires no external components. switching regulator. At very light load and no-load condi- tions, the buck will automatically skip cycles as needed
Main Control Loop
to maintain output regulation. An error amplifi er monitors the difference between an internal reference voltage and the voltage on the BUCKOUT
Soft-Start
pin. When the BUCKOUT voltage is below the reference, Soft-start in the buck regulator is accomplished by gradually the error amplifi er output voltage increases. When the increasing the maximum allowed peak inductor current BUCKOUT voltage exceeds the reference, the error ampli- over a 200μs period. This allows the output to rise slowly, fi er output voltage decreases. controlling the inrush current required to charge up the The error amplifi er output controls the peak inductor current output capacitor. A soft-start cycle occurs whenever the through the following mechanism: Paced by a free-running LTC3672B-2 is enabled, or after a fault condition has oc- 2.25MHz oscillator, the main P-channel MOSFET switch is curred (thermal shutdown or UVLO). 3672b2fa 7