Datasheet LTC3605 (Analog Devices) - 6

LTC3605
pin FuncTions RT (Pin 1):
Oscillator Frequency Programming Pin. Con-
VON (Pin 9):
On-Time Voltage Input. Voltage trip point for nect an external resistor (between 200k to 40k) from RT the on-time comparator. Tying this pin to the output volt- to SGND to program the frequency from 800kHz to 4MHz. age makes the on-time proportional to VOUT and keeps the Since the synchronization range is ±30% of set frequency, switching frequency constant at different VOUT. However, be sure that the set frequency is within this percentage when VON is <0.6V or >6V, then switching frequency will range of the external clock to ensure frequency lock. no longer remain constant.
PHMODE (Pin 2):
Control Input to Phase Selector. Deter-
PGND (Pin 10, Exposed Pad Pin 25):
Power Ground. mines the phase relationship between internal oscillator Return path of internal power MOSFETs. Connect this and CLKOUT. Tie it to INTVCC for 2-phase operation, tie it pin to the negative terminals of the input capacitor and to SGND for 3-phase operation, and tie it to INTVCC/2 for output capacitor. The exposed pad must be soldered to 4-phase operation. the PCB ground for electrical contact and rated thermal
MODE (Pin 3):
Operation Mode Select. Tie this pin to performance. INTVCC to force continuous synchronous operation at all
SW (Pins 11 to 16):
Switch Node Connection to External output loads. Tying it to SGND enables discontinuous mode Inductor. Voltage swing of SW is from a diode voltage operation at light loads. Do not float this pin. drop below ground to PVIN.
FB (Pin 4):
Output Feedback Voltage. Input to the error
PVIN (Pins 17, 18):
Power VIN. Input voltage to the on- amplifier that compares the feedback voltage to the internal chip power MOSFETs. 0.6V reference voltage. This pin is normally connected to
SV
a resistive divider from the output voltage.
IN (Pin 19):
Signal VIN. Filtered input voltage to the on-chip 3.3V regulator. Connect a (1Ω to 10Ω) resistor
TRACK/SS (Pin 5):
Output Tracking and Soft-Start Pin. between SVIN and PVIN and bypass to GND with a 0.1µF Allows the user to control the rise time of the output volt- capacitor. age. Putting a voltage below 0.6V on this pin bypasses
BOOST (Pin 20):
Boosted Floating Driver Supply for Inter- the internal reference input to the error amplifier, instead nal Top Power MOSFET. The (+) terminal of the bootstrap it servos the FB pin to the TRACK voltage. Above 0.6V, capacitor connects here. This pin swings from a diode the tracking function stops and the internal reference voltage drop below INTV resumes control of the error amplifier. There’s an internal CC up to PVIN + INTVCC. 2µA pull-up current from INTVCC on this pin, so putting a
INTVCC (Pin 21):
Internal 3.3V Regulator Output. The capacitor here provides soft-start function. internal power drivers and control circuits are powered from this voltage. Decouple this pin to power ground with
ITH (Pin 6):
Error Amplifier Output and Switching Regu- a minimum of 1µF low ESR ceramic capacitor. lator Compensation Point. The current comparator’s trip threshold is linearly proportional to this voltage, whose
SGND (Pin 22):
Signal Ground Connection. normal range is from 0.3V to 1.8V. Tying this pin to IN-
CLKOUT (Pin 23):
Output Clock Signal for PolyPhase TVCC activates internal compensation and output voltage Operation. The phase of CLKOUT with respect to CLKIN positioning, raising VOUT to 1.5% higher than the nominal is determined by the state of the PHMODE pin. CLKOUT’s value at IOUT = 0 and 1.5% lower at IOUT = 5A. peak-to-peak amplitude is INTVCC to GND.
RUN (Pin 7):
Run Control Input. Enables chip operation
CLKIN (Pin 24):
External Synchronization Input to Phase by tying RUN above 1.2V. Tying it below 1.1V shuts down Detector. This pin is internally terminated to SGND with 20k. the part. The phase-locked loop will force the top power NMOS’s
PGOOD (Pin 8):
Output Power Good with Open-Drain turn on signal to be synchronized with the rising edge of Logic. PGOOD is pulled to ground when the voltage on the the CLKIN signal. FB pin is not within ±10% of the internal 0.6V reference. 3605fh 6 For more information www.linear.com/LTC3605 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Typical Applications Package Description Revision History Typical Application Related Parts