Datasheet LT3653 (Analog Devices) - 9

LT3653
APPLICATIONS INFORMATION Battery Charger Operation
components, and tie this ground plane to system ground Connect the control node, V at one location, ideally at the ground terminal of the output C pin, of the LT3653 to the capacitor C2. Make the SW and BOOST nodes as short VC pin of the battery charger power path controller. The as possible. Include vias near the exposed GND pad of VC node is internally clamped; however, take care not to the LT3653 to help remove heat from the LT3653 to the overdrive the pin. The LT3653 is internally compensated ground plane. with a pole zero combination on the output of the gm amplifi er, G1. Check stability over the full input voltage
High Temperature Considerations
range, output load range and temperature. The die temperature of the LT3653 must not exceed Connect the HVOK node of the LT3653 to the high voltage the maximum rating of 125°C. This is generally not a present pin of the charger. This is the WALL pin on the concern unless the ambient temperature is above 85°C. LTC4098. The HVOK pin is capable of supplying up to 1mA For higher temperatures, take care in the layout of the of drive current. When the HVOK pin is low the LT3653 is circuit to ensure good heat sinking of the LT3653. Derate not switching and the system output cannot be supported the maximum load current as the ambient temperature by the LT3653 regulator. See the Typical Applications sec- approaches 125°C. The die temperature is calculated by tion for different confi gurations. multiplying the LT3653 power dissipation by the thermal resistance from junction to ambient. Power dissipation
PCB Layout
within the LT3653 is estimated by calculating the total Proper operation and minimum EMI requires a careful power loss from an effi ciency measurement and subtracting printed circuit board layout. Figure 1 shows the recom- the catch diode loss. Thermal resistance depends on the mended component placement with trace, ground plane layout of the circuit board, but 64°C/W is typical for the and via locations. Note that large, switched currents fl ow (2mm × 3mm) DFN (DCB) package. in the LT3653’s VIN and SW pins, the catch diode (D1) and the input capacitor (C1). Keep the loop formed by
Other Linear Technology Publications
these components as small as possible and tied to system Application Notes 19, 35 and 44 contain more detailed ground in only one place. Place these components, along descriptions and design information for Buck regulators with the inductor and output capacitor, on the same side and other switching regulators. The LT1376 data sheet of the circuit board, with their connections made on that has a more extensive discussion of output ripple, loop layer. Place a local, unbroken ground plane below these compensation and stability testing. V GND IN C1 TO CHARGER: 1 8 C3 HVOK 2 7 3 6 VC 4 5 C2 RILIM VOUT 3653 F01
Figure 1. LT3653 PCB Layout
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