Datasheet ADP5020 (Analog Devices) - 3

ADP5020 FUNCTIONAL BLOCK DIAGRAM VDD3 VDD2 VDD1 VDDA SW1 XSHTDN RESET UVLO BUCK 1 VOUT1 VOUT1 PGND1 SCL I2C SDA SW2 BUCK 2 VDD_IO CONTROL VOUT2 LOGIC EN/GPIO PGND2 SYNC THERMAL LDO SHUTDOWN VOUT3 BUCK1_EN VDDA HOUSE- SEQUENCER BUCK2_EN KEEPING LDO_EN
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DGND AGND
07 Figure 2. Rev. 0 | Page 3 of 28 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATIONS CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS SWITCHING SPECIFICATIONS DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 1 REGULATOR DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 2 REGULATOR VOUT3 SPECIFICATIONS, LOW DROPOUT (LDO) REGULATOR I2C TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Thermal Data ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT OPERATION INTERNAL COMPENSATION CURRENT LIMITING AND SHORT-CIRCUIT PROTECTION SYNCHRONIZATION I2C INTERFACE UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN CONTROL REGISTERS DEVICE ADDRESS REGISTER MAP REGISTER DESCRIPTIONS User Accessible Registers POWER-UP/POWER-DOWN SEQUENCE SEQUENCER DEFAULT POWER-ON SEQUENCE WITH EN PIN Activation Waveforms POWER-ON SEQUENCE USING THE I2C INTERFACE POWER-UP/POWER-DOWN STATE FLOW APPLICATIONS INFORMATION POWER GOOD STATUS XSHTDN LOGIC COMPONENTS SELECTION Buck Inductor Input Capacitor Selection Output Capacitor Selection LDO INPUT FILTER LAYOUT RECOMMENDATIONS APPLICATIONS SCHEMATIC PCB BOARD LAYOUT RECOMMENDATIONS EXTERNAL COMPONENT LIST OUTLINE DIMENSIONS ORDERING GUIDE