Datasheet LT3688 (Analog Devices) - 10

LT3688
OPERATION
The LT3688 is a constant-frequency, current mode step- optimize effi ciency, the LT3688 automatically switches to down regulator with two reset timers and a watchdog Burst Mode operation in light load situations. Between timer that perform microprocessor supervisory functions. bursts, all circuitry associated with controlling the output Operation can be best understood by referring to the Block switch is shut down, reducing the input supply current to Diagram. Keeping the EN/UVLO pin at ground completely 115μA in a typical application. shuts off the part drawing minimal current from the VIN A comparator monitors the current fl owing through the source. To turn on the internal bandgap and the rest of the catch diode via the DA pin. This comparator delays switch- logic circuitry, raise the EN/UVLO pin above the accurate ing if the diode current goes higher than 1.2A (typical) threshold of 1.25V. Also, VIN needs to be higher than 3.5V during a fault condition such as a shorted output with high for the part to start switching. input voltage. Switching will only resume once the diode current has fallen below the 1.2A limit. This way the DA
Switching Regulator Operation
comparator regulates the valley current of the inductor An oscillator, with frequency set by RT, enables an RS fl ip to 1.2A during short circuit. This will ensure that the part fl op, turning on the internal power switch. An amplifi er will survive a short-circuit event. and comparator monitor the current fl owing between the VIN and SW pins, turning the switch off when this cur-
Power-On Reset and Watchdog Timer Operation
rent reaches a level determined by the voltage at VC. An The LT3688 has two power-on reset comparators that error amplifi er measures the output voltage through an monitor the regulated output voltages. If V external resistor divider tied to the FB pin and servos the OUT is 10% below the regulation value, the RST pin is pulled low. Once VC voltage. If the error amplifi er’s output increases, more the output voltage crosses over 90% of the regulation current is delivered to the output; if it decreases, less value, a reset timer is started and RST is released after current is delivered. An active clamp on the VC voltage the programmed reset delay time. The reset delay is provides current limit. The VC voltage is also controlled programmable through the C by the internal soft-start circuit during start-up or after a POR pin. fault condition takes place. The watchdog typically monitors a microprocessor’s activity. The watchdog can be enabled or disabled by ap- An internal regulator provides power to the control cir- plying a logic signal to the WDE pin. The watchdog timer cuitry. The internal regulator normally draws current from requires successive negative edges on the WDI pin to the VIN pin, but if the BIAS pin is connected to an external come within a programmed time window to keep WDO voltage higher than 3V, bias current will be drawn from the from going low. If the time between the two negative WDI external source (typically the regulated output voltage). edges is too short or too long, then the WDO pin will be This improves effi ciency. The BIAS pin also provides a pulled low. When the WDO pin goes low, it stays low for current path to the internal boost diode that charges up a time period equivalent to 1/8th of the watchdog window the boost capacitor. The switch driver operates either from upper boundary. The WDO pin will go high again once the the VIN or from the BST pin. An external capacitor is used timer expires or if the RST pin goes low. The watchdog to generate a voltage at the BST pin that is higher than window upper and lower boundaries can be set through the VIN supply. This allows the driver to fully saturate the the C internal NPN power switch for effi cient operation. To further WDT pin. 3688f 10