Datasheet ADP5042 (Analog Devices)

FabricanteAnalog Devices
DescripciónMicro PMU with 0.8 A Buck, Two 300 mA LDOs, Supervisory, Watchdog and Manual Reset
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RevisiónB
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Micro PMU with 0.8 A Buck, Two 300 mA LDOs. Supervisory, Watchdog, and Manual Reset. Data Sheet. ADP5042. FEATURES

Datasheet ADP5042 Analog Devices, Revisión: B

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Micro PMU with 0.8 A Buck, Two 300 mA LDOs Supervisory, Watchdog, and Manual Reset Data Sheet ADP5042 FEATURES HIGH LEVEL BLOCK DIAGRAM Input voltage range: 2.3 V to 5.5 V RFILT = 30Ω AVIN L1 One 0.8 A buck regulator 1µH AVIN SW VOUT1 AT Two 300 mA LDOs VIN1 = 2.3V VIN1 VOUT1 800mA C6 BUCK TO 5.5V C5 PGND 10µF 20-lead, 4 mm × 4 mm LFCSP package 4.7µF EN_BK ON FPWM MODE EN1 OFF Initial regulator accuracy: ±1% PSM/PWM LDO1 VOUT2 V VIN2 = 1.7V VIN2 OUT2 AT Overcurrent and thermal protection (DIGITAL) 300mA TO 5.5V C1 EN_LDO1 C2 R 1µF Soft start ON O 1µF EN2 WSTAT S OFF AVIN S nRSTO Undervoltage lockout CE ISOR V WDI1 RO R P Open drain processor reset with threshold monitoring MR E WDI2 P RO ON SU IC ±1.5% threshold accuracy over the full temperate range EN3 M OFF EN_LDO2 Guaranteed reset output valid to V VIN3 = 1.7V VIN3 VOUT3 V CC = 1 V LDO2 OUT3 AT TO 5.5V C3 (ANALOG) 300mA Dual watchdog for secure systems C4 1µF 1µF Watchdog 1 controls reset AGND
-001 1 1 8
Watchdog 2 controls reset and regulators power cycle
08 Figure 1.
Buck key specifications Current mode topology for excellent transient response 3 MHz operating frequency Uses tiny multilayer inductors and capacitors Mode pin selects forced PWM or auto PFM/PSM modes 100% duty cycle low dropout mode LDOs key specifications Low VIN from 1.7 V to 5.5 V Stable with1 μF ceramic output capacitors High PSRR, 60 dB PSRR up to 1 kHz/10 kHz Low output noise 110 μV rms typical output noise at VOUT = 2.8 V Low dropout voltage: 150 mV at 300 mA load −40°C to +125°C junction temperature range GENERAL DESCRIPTION
The ADP5042 combines one high performance buck regulator The low quiescent current, low dropout voltage, and wide input and two low dropout (LDO) regulators in a small 20-lead voltage range of the ADP5042 LDOs extend the battery life of LFCSP to meet demanding performance and board space portable devices. The two LDOs maintain power supply requirements. rejection greater than 60 dB for frequencies as high as 10 kHz The high switching frequency of the buck regulator enables while operating with a low headroom voltage. use of tiny multilayer external components and minimizes the Each regulator is activated by a high level on the respective board space. enable pin. The ADP5042 is available with factory programmable The MODE pin selects the buck mode of operation. When set default output voltages and can be set to a wide range of options. to logic high, the buck regulators operate in forced PWM mode. The ADP5042 contains supervisory circuits that monitor When the MODE pin is set to logic low, the buck regulators power supply voltage levels and code execution integrity in operate in PWM mode when the load is around the nominal microprocessor-based systems. They also provide power-on value. When the load current falls below a predefined threshold reset signals. An on-chip dual watchdog timer can reset the the regulator operates in power save mode (PSM) improving microprocessor or power cycle the system (Watchdog 2) if it the light load efficiency. fails to strobe within a preset timeout period.
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2010-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES HIGH LEVEL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS GENERAL SPECIFICATION SUPERVISORY SPECIFICATION BUCK SPECIFICATIONS LDO1, LDO2 SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Thermal Protection Undervoltage Lockout Enable/Shutdown BUCK SECTION Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Short-Circuit Protection Soft Start Current Limit 100% Duty Operation LDO SECTION SUPERVISORY SECTION Reset Output Manual Reset Input Watchdog 1 Input Watchdog 2 Input Watchdog Status Indicator APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Inductor Output Capacitor Input Capacitor LDO CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties SUPERVISORY SECTION Watchdog 1 Input Current Negative-Going VCC Transients Watchdog Software Considerations PCB LAYOUT GUIDELINES EVALUATION BOARD SCHEMATICS AND ARTWORK SUGGESTED LAYOUT BILL OF MATERIALS APPLICATION DIAGRAM FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE