Datasheet LTC3104 (Analog Devices) - 8

LTC3104
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted LDO Output Voltage LDO Ripple Rejection Load Step (Automatic Burst Mode Operation)
VOUT VLDO 50mV/DIV 20mV/DIV AC-COUPLED AC-COUPLED VLDO 20mV/DIV AC-COUPLED IL ILOAD 200mA/DIV 10mA/DIV 20ms/DIV 3104 G31 50µs/DIV 3104 G32 ILOAD = 10mA ILOAD = LOAD STEP, NO LOAD TO 10mA ILDO = 1mA VLDO = 1.8V VLDO = 1.8V, VIN = 10V VIN(LDO) = VIN = 10V VIN(LDO) = VOUT = 2.5V CIN = 10µF CIN = 10µF, COUT = 22µF COUT = 10µF CLDO = 4.7µF, L = 10µH
PIN FUNCTIONS (DFN/MSOP) MODE (Pin 1/Pin 2):
Logic-Controlled Input to Select
NC (Pin 8/Pins 1, 9, 16):
No Connect Pin(s) Must Be Tied Mode of Operation. Forcing this pin high commands high to GND. efficiency automatic Burst Mode operation where the buck
V
will automatically transition from PWM operation at heavy
CC (Pin 9/Pin 10):
Internally Regulated Supply Rail. Internal power rail regulated off of V load to Burst Mode operation at light loads. Forcing this IN to power control circuitry. Decouple with a 1µF or larger ceramic capacitor pin low commands low noise, fixed frequency, forced placed as close to the part as possible. continuous operation.
RUN (Pin 10/Pin 11):
Run Pin Comparator Input. A voltage
VIN (Pin 2/Pin 3):
Main Supply Pin. Decouple with a 10µF greater than 0.85V will enable the IC. Tie this pin to V or larger ceramic capacitor. The capacitor should be as IN to enable the IC or connect to an external resistor divider from close to the part as possible. VIN to provide an accurate undervoltage lockout threshold.
SW (Pin 3/Pin 4):
Switch Pin Connects to the Inductor. 60mV of hysteresis is provided internally. This pin connects to the drains of the internal main and
FB (Pin 11/Pin 12):
Feedback Input to Error Amplifier. synchronous power MOSFET switches. The resistor divider connected to this pin sets the buck
BST (Pin 4/Pin 5):
Bootstrapped Floating Supply for High converter output voltage. Side Gate Drive. Connect to SW through a 22nF (minimum)
FBLDO (Pin 12/Pin 13):
Feedback Input to the LDO Error capacitor. The capacitor must be connected between BST Amplifier. The resistor divider on this pin sets the LDO and SW and be located as close as possible to the part output voltage. as possible.
V GND (Pin 5/Pin 6):
Power Ground.
LDO (Pin 13/Pin 14):
LDO Regulator Output. Decouple with a 4.7µF or larger ceramic capacitor placed as close
RUNLDO (Pin 6/Pin 7):
Logic-Controlled LDO Enable Pin. to the part as possible. This pin may be tied to VIN to enable the LDO.
VINLDO (Pin 14/Pin 15):
LDO Supply Pin (15V Maximum).
PGOOD (Pin 7/Pin 8):
Open-drain output that is pulled Decouple with a 10µF or larger ceramic capacitor. to ground when the feedback voltage falls 10% (typical)
GND (Exposed Pad Pin 15/Exposed Pad Pin 17):
Back- below the regulation point, during a thermal shutdown pad Ground Common. This pad must be soldered to the event or if the converter is disabled. The PGOOD output PC board and connected to the ground plane for optimal is valid 1ms after the buck converter is enabled. thermal performance. 3104fa 8 For more information www.linear.com/LTC3104 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts