Datasheet ADP2323 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | Dual 3 A, 20 V Synchronous Step-Down Regulator with Integrated High-Side MOSFET |
| Páginas / Página | 32 / 6 — ADP2323. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 2. THERMAL … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 992 Kb |
| Idioma del documento | Inglés |
ADP2323. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 2. THERMAL RESISTANCE. Parameter. Rating. Boundary Condition
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ADP2323 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. THERMAL RESISTANCE Parameter Rating
θJA is specified for the worst-case conditions, that is, a device PVIN1, PVIN2, EN1, EN2 −0.3 V to +22 V soldered in a circuit board for surface-mount packages. SW1, SW2 −1 V to +22 V
Boundary Condition
BST1, BST2 V + 6 V SW θ FB1, FB2, SS1, SS2,COMP1, COMP2, −0.3 V to +6 V JA is measured using natural convection on a JEDEC 4-layer PGOOD1, PGOOD2, TRK1, TRK2, SCFG, board, and the exposed pad is soldered to the printed circuit SYNC, RT, MODE board (PCB) with thermal vias. INTVCC, VDRV, DL1, DL2 −0.3 V to +6 V
Table 3. Thermal Resistance
PGND to GND −0.3 V to +0.3 V
Package Type θ Unit
Temperature Range
JA
32-Lead LFCSP_WQ 32.7 °C/W Operating (Junction) −40°C to +125°C Storage −65°C to +150°C
ESD CAUTION
Soldering Conditions JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 6 of 32 Document Outline Features Applications Typical Application Circuit General Description Revision History Functional Block Diagram Specifications Absolute Maximum Ratings Thermal Resistance Boundary Condition ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Control Scheme PWM Mode PFM Mode Precision Enable/Shutdown Separate Input Voltages Internal Regulator (INTVCC) Bootstrap Circuitry Low-Side Driver Oscillator Synchronization Soft Start Peak Current-Limit and Short-Circuit Protection Voltage Tracking Parallel Operation Power Good Overvoltage Protection Undervoltage Lockout Thermal Shutdown Applications Information ADIsimPower Design Tool Input Capacitor Selection Output Voltage Setting Voltage Conversion Limitations Current-Limit Setting Inductor Selection Output Capacitor Selection Low-Side Power Device Selection Programming UVLO Input Compensation Components Design Design Example Output Voltage Setting Current-Limit Setting Frequency Setting Inductor Selection Output Capacitor Selection Low-Side MOSFET Selection Compensation Components Soft Start Time Programming Input Capacitor Selection External Components Recommendation Typical Application Circuits Outline Dimensions Ordering Guide
θJA is specified for the worst-case conditions, that is, a device PVIN1, PVIN2, EN1, EN2 −0.3 V to +22 V soldered in a circuit board for surface-mount packages. SW1, SW2 −1 V to +22 V
Boundary Condition
BST1, BST2 V + 6 V SW θ FB1, FB2, SS1, SS2,COMP1, COMP2, −0.3 V to +6 V JA is measured using natural convection on a JEDEC 4-layer PGOOD1, PGOOD2, TRK1, TRK2, SCFG, board, and the exposed pad is soldered to the printed circuit SYNC, RT, MODE board (PCB) with thermal vias. INTVCC, VDRV, DL1, DL2 −0.3 V to +6 V
Table 3. Thermal Resistance
PGND to GND −0.3 V to +0.3 V
Package Type θ Unit
Temperature Range
JA
32-Lead LFCSP_WQ 32.7 °C/W Operating (Junction) −40°C to +125°C Storage −65°C to +150°C
ESD CAUTION
Soldering Conditions JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 6 of 32 Document Outline Features Applications Typical Application Circuit General Description Revision History Functional Block Diagram Specifications Absolute Maximum Ratings Thermal Resistance Boundary Condition ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Control Scheme PWM Mode PFM Mode Precision Enable/Shutdown Separate Input Voltages Internal Regulator (INTVCC) Bootstrap Circuitry Low-Side Driver Oscillator Synchronization Soft Start Peak Current-Limit and Short-Circuit Protection Voltage Tracking Parallel Operation Power Good Overvoltage Protection Undervoltage Lockout Thermal Shutdown Applications Information ADIsimPower Design Tool Input Capacitor Selection Output Voltage Setting Voltage Conversion Limitations Current-Limit Setting Inductor Selection Output Capacitor Selection Low-Side Power Device Selection Programming UVLO Input Compensation Components Design Design Example Output Voltage Setting Current-Limit Setting Frequency Setting Inductor Selection Output Capacitor Selection Low-Side MOSFET Selection Compensation Components Soft Start Time Programming Input Capacitor Selection External Components Recommendation Typical Application Circuits Outline Dimensions Ordering Guide