Datasheet ADP5023 (Analog Devices)

Dual 3 MHz, 800 mA Buck Regulators with One 300 mA LDO Data Sheet ADP5023 FEATURES
above a predefined threshold. When the load current fal s below
Main input voltage range: 2.3 V to 5.5 V
a predefined threshold, the regulator operates in power save
Two 800 mA buck regulators and one 300 mA LDO
mode (PSM) improving the light-load efficiency.
24-lead, 4 mm × 4 mm LFCSP package Table 1. Family Models Regulator accuracy: ±1.8% Maximum Factory programmable or external adjustable VOUTx Model Channels Current Package 3 MHz buck operation with forced PWM and auto PWM/PSM
ADP5023 2 buck, 1 LDO 800 mA, LFCSP (CP-24-10)
modes
300 mA
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V
ADP5024 2 buck, 1 LDO 1.2 A, 300 mA LFCSP (CP-24-10)
LDO: output voltage range from 0.8 V to 5.2 V
ADP5034 2 buck, 2 LDOs 1.2 A, 300 mA LFCSP (CP-24-10), TSSOP (RE-28-1)
LDO: input supply voltage from 1.7 V to 5.5 V
ADP5037 2 buck, 2 LDOs 800 mA, LFCSP (CP-24-10)
LDO: high PSRR and low output noise
300 mA
APPLICATIONS
ADP5033 2 buck, 2 LDOs 800 mA, WLCSP (CB-16-8) with 2 EN pins 300 mA
Power for processors, ASIC, FPGAs, and RF chipsets
ADP5040 1 buck, 2 LDOs 1.2 A, 300 mA LFCSP (CP-20-10)
Portable instrumentation and medical devices
ADP5041 1 buck, 2 LDOs with 1.2 A, 300 mA LFCSP (CP-20-10)
Space constrained devices
supervisory, watch- dog, manual reset
GENERAL DESCRIPTION
The two bucks operate out of phase to reduce the input capaci- The ADP5023 combines two high performance buck regulators tor requirement. The low quiescent current, low dropout voltage, and one low dropout (LDO) regulator in a small, 24-lead 4 mm × and wide input voltage range of the ADP5023 LDO extends the 4 mm LFCSP to meet demanding performance and board space battery life of portable devices. The ADP5023 LDO maintains requirements. power supply rejection greater than 60 dB for frequencies as The high switching frequency of the buck regulators enables tiny high as 10 kHz while operating with a low headroom voltage. multilayer external components and minimizes the board space. Regulators in the ADP5023 are activated though dedicated When the MODE pin is set high, the buck regulators operate in enable pins. The default output voltages can be externally set in forced PWM mode. When the MODE pin is set low, the buck the adjustable version or factory programmable to a wide range regulators operate in PWM mode when the load current is of preset values in the fixed voltage version.
TYPICAL APPLICATION CIRCUIT AVIN HOUSEKEEPING CFILT VOUT1 0.1µF L1 1µH VIN1 2.3V TO SW1 VOUT1 AT 5.5V 800mA C1 FB1 R1 BUCK1 4.7µF C5 R2 10µF ON EN1 PGND1 EN1 OFF MODE PWM MODE PSM/PWM VOUT2 VIN2 MODE L2 1µH SW2 V C2 OUT2 AT 4.7µF 800mA BUCK2 FB2 R3 C6 EN2 R4 ON EN2 PGND2 10µF OFF EN3 VOUT3 V EN3 OUT3 AT VIN3 300mA 1.7V TO LDO FB3 R5 5.5V C7 C3 1µF 1µF R6 ADP5023
001
AGND
09889- Figure 1.
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Document Outline Features Applications General Description Typical Application Circuit Revision History Specifications General Specifications BUCK1 and BUCK2 Specifications LDO Specifications Input and Output Capacitor, Recommended Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Management Unit Thermal Protection Undervoltage Lockout Enable/Shutdown BUCK1 and BUCK2 Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Oscillator/Phasing of Inductor Switching Short-Circuit Protection Soft Start Current Limit 100% Duty Operation Active Pull-Downs LDO Applications Information Buck External Component Selection Feedback Resistors Inductor Output Capacitor Input Capacitor LDO External Component Selection Feedback Resistors Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Power Dissipation and Thermal Considerations Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature PCB Layout Guidelines Typical Application Schematics Bill of Materials Outline Dimensions Ordering Guide