Datasheet ADP5050 (Analog Devices) - 2

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ADP5050 Data Sheet TABLE OF CONTENTS
Features .. 1 LDO Regulator ... 26 Applications ... 1 I2C Interface .. 27 General Description ... 1 SDA and SCL Pins .. 27 Typical Application Circuit ... 1 I2C Addresses .. 27 Revision History ... 3 Self-Clear Register Bits .. 27 Detailed Functional Block Diagram .. 4 I2C Interface Timing Diagrams .. 28 Specifications ... 5 Applications Information .. 29 Buck Regulator Specifications .. 6 ADIsimPower Design Tool ... 29 LDO Regulator Specifications .. 8 Programming the Adjustable Output Voltage .. 29 I2C Interface Timing Specifications ... 9 Voltage Conversion Limitations ... 29 Absolute Maximum Ratings .. 10 Current-Limit Setting .. 29 Thermal Resistance .. 10 Soft Start Setting ... 30 ESD Caution .. 10 Inductor Selection .. 30 Pin Configuration and Function Descriptions ... 11 Output Capacitor Selection... 30 Typical Performance Characteristics ... 13 Input Capacitor Selection .. 31 Theory of Operation .. 19 Low-Side Power Device Selection .. 31 Buck Regulator Operational Modes ... 19 Programming the UVLO Input .. 31 Adjustable and Fixed Output Voltages .. 20 Compensation Components Design ... 32 Dynamic Voltage Scaling (DVS) .. 20 Power Dissipation... 32 Internal Regulators (VREG and VDD) ... 20 Junction Temperature .. 33 Separate Supply Applications .. 20 Design Example .. 34 Low-Side Device Selection .. 21 Setting the Switching Frequency .. 34 Bootstrap Circuitry .. 21 Setting the Output Voltage .. 34 Active Output Discharge Switch .. 21 Setting the Current Limit .. 34 Precision Enabling .. 21 Selecting the Inductor .. 34 Oscillator ... 21 Selecting the Output Capacitor .. 35 Synchronization Input/Output ... 22 Selecting the Low-Side MOSFET ... 35 Soft Start .. 23 Designing the Compensation Network ... 35 Parallel Operation... 23 Selecting the Soft Start Time... 35 Startup with Precharged Output .. 23 Selecting the Input Capacitor ... 35 Current-Limit Protection .. 24 Recommended External Components .. 36 Frequency Foldback ... 24 Circuit Board Layout Recommendations ... 37 Hiccup Protection .. 24 Typical Application Circuits ... 38 Latch-Off Protection .. 24 Register Map ... 41 Undervoltage Lockout (UVLO) ... 25 Detailed Register Descriptions ... 42 Power-Good Function ... 25 Register 1: PCTRL (Channel Enable Control), Address 0x01 42 Interrupt Function .. 25 Register 2: VID1 (VID Setting for Channel 1), Address 0x02 Thermal Shutdown ... 26 ... 42 Overheat Detection .. 26 Register 3: VID23 (VID Setting for Channel 2 and Channel 3), Address 0x03 ... 43 Low Input Voltage Detection .. 26 Rev. C | Page 2 of 55 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO REGULATOR SPECIFICATIONS I2C INTERFACE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES DYNAMIC VOLTAGE SCALING (DVS) INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION INTERRUPT FUNCTION THERMAL SHUTDOWN OVERHEAT DETECTION LOW INPUT VOLTAGE DETECTION LDO REGULATOR I2C INTERFACE SDA AND SCL PINS I2C ADDRESSES SELF-CLEAR REGISTER BITS I2C INTERFACE TIMING DIAGRAMS APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown LDO Regulator Power Dissipation JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS REGISTER MAP DETAILED REGISTER DESCRIPTIONS REGISTER 1: PCTRL (CHANNEL ENABLE CONTROL), ADDRESS 0x01 REGISTER 2: VID1 (VID SETTING FOR CHANNEL 1), ADDRESS 0x02 REGISTER 3: VID23 (VID SETTING FOR CHANNEL 2 AND CHANNEL 3), ADDRESS 0x03 REGISTER 4: VID4 (VID SETTING FOR CHANNEL 4), ADDRESS 0x04 REGISTER 5: DVS_CFG (DVS CONFIGURATION FOR CHANNEL 1 AND CHANNEL 4), ADDRESS 0x05 REGISTER 6: OPT_CFG (FPWM/PSM MODE AND OUTPUT DISCHARGE FUNCTION CONFIGURATION), ADDRESS 0x06 REGISTER 7: LCH_CFG (SHORT-CIRCUIT LATCH-OFF AND OVERVOLTAGE LATCH-OFF CONFIGURATION), ADDRESS 0x07 REGISTER 8: SW_CFG (SWITCHING FREQUENCY AND PHASE SHIFT CONFIGURATION), ADDRESS 0x08 REGISTER 9: TH_CFG (TEMPERATURE WARNING AND LOW VIN WARNING THRESHOLD CONFIGURATION), ADDRESS 0x09 REGISTER 10: HICCUP_CFG (HICCUP CONFIGURATION), ADDRESS 0x0A REGISTER 11: PWRGD_MASK (CHANNEL MASK CONFIGURATION FOR PWRGD PIN), ADDRESS 0x0B REGISTER 12: LCH_STATUS (LATCH-OFF STATUS READBACK), ADDRESS 0x0C REGISTER 13: STATUS_RD (STATUS READBACK), ADDRESS 0x0D REGISTER 14: INT_STATUS (INTERRUPT STATUS READBACK), ADDRESS 0x0E REGISTER 15: INT_MASK (INTERRUPT MASK CONFIGURATION), ADDRESS 0x0F REGISTER 17: DEFAULT_SET (DEFAULT RESET), ADDRESS 0x11 FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE