Datasheet LTC3375 (Analog Devices) - 5

LTC3375
e lecTrical characTerisTics The
l
denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VIN1-8 = 3.3V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VPGOOD(FALL) Falling PGOOD Threshold Voltage % of Full-Scale (1, 1, 1, 1) Reference Voltage 92.5 % VPGOOD(HYS) PGOOD Hysteresis % of Regulated VFB 1 %
Buck Regulators Combined
IFWD2 PMOS Current Limit 2 Buck Converters Combined (Note 5) 4.6 A IFWD3 PMOS Current Limit 3 Buck Converters Combined (Note 5) 6.9 A IFWD4 PMOS Current Limit 4 Buck Converters Combined (Note 5) 9.2 A
VCC Regulator
VFBVCC FBVCC Regulation Voltage 1.17 1.2 1.23 V RREG Pull-Down Resistance for VCC 200 Ω (Regulator) VVSHNT_MAX VSHNT Clamp Voltage ISHNT = 2mA, FBVCC = 0V 6.1 V RCLAMP Pull-Down Resistance for VSHNT (Clamp) 200 Ω
I2C Port
ADDRESS I2C Address l 0110100[R/WB] VIH Input High Voltage SDA/SCL l 1.2 V VIL Input Low Voltage SDA/SCL l 0.4 V IIH Input High Current SDA/SCL 50 nA IIL Input Low Current SDA/SCL 50 nA VOL_SDA SDA Output Low Voltage ISDA = 3mA 0.4 V fSCL Clock Operating Frequency 400 kHz tBUF Bus Free Time Between Stop and Start 1.3 µs Condition tHD_SDA Hold Time After Repeated Start 0.6 µs Condition tSU_STA Repeated Start Condition Set-Up Time 0.6 µs tSU_STO Stop Condition Set-Up Time 0.6 µs tHD_DAT(O) Data Hold Time Output 0 900 ns tHD_DAT(I) Data Hold Time Input 0 ns tSU_DAT Data Set-Up Time 250 ns tLOW SCL Clock Low Period 1.3 µs tHIGH SCL Clock High Period 0.6 µs tf Clock/Data Fall Time CB = Capacitance of One Bus Line (pF) 20+0.1CB 300 ns tr Clock/Data Rise Time CB = Capacitance of One Bus Line (pF) 20+0.1CB 300 ns
Interface Logic Pins (ON, KILL, RST, IRQ, PB, WDI, WDO)
IOH Output High Leakage Current ON, RST, IRQ, WDO 5.5V at Pin -1 1 µA VOL Output Low Voltage ON, RST, IRQ, WDO 3mA Into Pin 0.1 0.4 V VIH Input High Threshold KILL, PB, WDI l 1.2 V VIL Input Low Threshold KILL, PB, WDI l 0.4 V tWDI Time From Last WDI 1.5 sec tWDO WDO Low Time Absent a Transition at WDI 200 ms tWDRESET Time From a WDI Transition Until the 2 µs WD Timer Is Reset 3375fd For more information www.linear.com/3375 5 Document Outline Features Applications Description Typical Application Table of Contents Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Application Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Buck Switching Regulators Buck Regulators with Combined Power Stages Pushbutton Interface Power-Up and Power-Down Via Pushbutton Power-Up and Power-Down Via Enable Pin or I2C I2C Interface I2C Bus Speed I2C Start and Stop Conditions I2C Byte Format I2C Acknowledge I2C Slave Address I2C Sub-Addressed Writing I2C Bus Write Operation I2C Bus Read Operation Error Condition Reporting Via RST and IRQ Pins Temperature Monitoring and Overtemperature Protection RESET_ALL Functionality Programming the Operating Frequency VCC Shunt Regulator Watchdog Timer Applications Information Buck Switching Regulator Output Voltage and Feedback Network Buck Regulators Combined Buck Regulators VCC Shunt Regulator Input and Output Decoupling Capacitor Selection Choosing the CT Capacitor Programming the Global Register Programming the RST and IRQ Mask Registers Status Byte Read Back Typical Applications Package Description Typical Application Related Parts