Datasheet ADP5080 (Analog Devices) - 3

Data Sheet ADP5080 SPECIFICATIONS
TJ = 25°C, VVBATT = 7.2 V, VVREG1 = VVDRx = 5 V, VVREG2 = VVDDIO = 3.3 V, unless otherwise noted.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE VBATT VVBATT 4.0 15 V Applies to PVIN1, PVIN2, PVIN3, PVIN4, PVIN5, and PVIN6 VILDO7 VVILDO7 5 25 V VDDIO VVDDIO 1.6 3.6 V QUIESCENT CURRENT Operating Quiescent Current IQ (VIN) 8 11 mA All channels on, nonswitching VDDIO IQ (VDDIO_OP) 0.2 µA VVDDIO = VSCL = VSDA = 3.3 V Standby Current IQ (VBATT_STNBY1) 12 20 µA Includes LDO1 and LDO2, EN low IQ (VBATT_STNBY2) 1.25 mA All channels off, EN high, SEL_FSW = 1, FREQ_CP = 01 UNDERVOLTAGE LOCKOUT UVLO UVLO Rising Threshold VUVLO (R) 3.45 3.7 3.85 V At PVIN1 UVLO Falling Threshold VUVLO (F) 3.45 3.55 V At PVIN1 VBATT UVLO Threshold VUVLO (BATT) 3.3 V At VBATT, falling Reset Threshold VUVLO (POR) 2.4 V At VREG2, falling OSCILLATOR CIRCUIT Switching Frequency fSW 1.98 2.0 2.02 MHz ROSC = 100 kΩ, SEL_FSW = 0 1.48 1.5 1.52 MHz ROSC = 100 kΩ, SEL_FSW = 1 SYNC Pin, Input Clock Frequency Range fSYNC 0.5 2.0 MHz ROSC = 100 kΩ Minimum On Pulse Width tSYNC_MIN_ON 100 ns Minimum Off Pulse Width tSYNC_MIN_OFF 100 ns High Logic VH (SYNC) 0.8 × VVREG2 V VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C Low Logic VL (SYNC) 0.3 × VVREG2 V VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C LOGIC INPUTS EN Pin High Level Threshold VIH (EN) 2.15 V VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C Low Level Threshold VIL (EN) 1.45 V VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C EN34 Pin High Level Threshold VIH (EN34) 1.25 V VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C Low Level Threshold VIL (EN34) 0.70 V VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C SCL and SDA Pins High Level Threshold VIH (I2C) 0.75 × VVDDIO V VVDDIO = 3.3 V, −25°C ≤ TJ ≤ +85°C Low Level Threshold VIL (I2C) 0.3 × VVDDIO V VVDDIO = 3.3 V, −25°C ≤ TJ ≤ +85°C LOGIC OUTPUTS SDA Pin Low Level Output Voltage VOL (SDA) 0.4 V 3.0 mA sink current, −25°C ≤ TJ ≤ +85°C Leakage Current ILEAK (SDA) 10 nA VSDA = 3.3 V CLKO Pin High Level Output Voltage VOH (CLKO) VVREG2 − 0.4 V 3.0 mA sink current, −25°C ≤ TJ ≤ +85°C Low Level Output Voltage VOL (CLKO) 0.4 V 3.0 mA sink current, −25°C ≤ TJ ≤ +85°C FAULT Pin Low Level Output Voltage VOL (FAULT) 0.4 V 3.0 mA source current, −25°C ≤ TJ ≤ +85°C Leakage Current ILEAK ( = 3.3 V FAULT) 10 nA VFAULT Rev. A | Page 3 of 64 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Housekeeping Block Specifications DC-to-DC Converter Block Specifications Linear Regulator Block Specifications I2C Interface Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Application Circuit Theory of Operation UVLO and POR Undervoltage Lockout (UVLO) Power-On Reset (POR) Discharge Switch Keep-Alive LDO Linear Regulators LDO1 VISW1 Input Current Limit for LDO1 Discharge Switch for LDO1 LDO2 VISW2 Input Current Limit for LDO2 Discharge Switch for LDO2 DC-to-DC Converter Channels Channel 1, Channel 2, and Channel 3: Buck Regulators with Flex-Mode Architecture Selecting the Output Voltage, Channel 1 to Channel 3 Current-Limit Protection, Channel 1 to Channel 3 Discharge Switch, Channel 1 to Channel 3 Gate Scaling (Channel 1 Only) Dynamic Voltage Scaling (DVS) Function Channel 4 and Channel 5: Current Mode Buck Regulators Selecting the Output Voltage, Channel 4 and Channel 5 Current-Limit Protection, Channel 4 and Channel 5 Discharge Switch, Channel 4 and Channel 5 Channel 6: Buck or Buck Boost Regulator Buck Only Configuration Buck Boost Configuration Selecting the Output Voltage, Channel 6 Current-Limit Protection, Channel 6 Discharge Switch, Channel 6 Light Load and Other Modes of Operation for the DC-to-DC Converter Channels Slew Rate Adjustment Forced PWM (FPWM) Mode Auto DCM Auto PSM Selecting Light Load Switching Modes Switching Clock External Synchronization Mode Selecting the Internal Clock Frequency Selecting the External Resistor Phase Shifting CLKO Pin Soft Start Function Channel 7: High Voltage LDO Regulator Selecting the Output Voltage, Channel 7 Discharge Switch, Channel 7 Charge Pump Charge Pump Switching Frequency Capacitor Selection Protection Diode Using the Charge Pump as the Channel 7 Input Supply Enabling and Disabling the Output Channels Sequencer Mode Manual Mode EN Function EN34 Function Power-Good Function Fault Function Undervoltage Protection (UVP) UVP Detection Delay Channel 5 Standalone Undervoltage Detection Option Recovering from UVP Overvoltage Protection (OVP) OVP Detection Delay Recovering from OVP Applications Information Component Selection for the Buck and Buck Boost Regulators Setting the Output Voltage (Adjustable Mode Channels) Selecting the Inductor Selecting the Input Capacitor Selecting the Output Capacitor Component Selection for the LDO Regulators Selecting the Capacitors PCB Layout Recommendations Sensitive Signal Treatment Grounding External Component Placement and Signal Routing Thermal Considerations I2C Interface SDA and SCL Pins I2C Address Self-Clearing Register Bits I2C Interface Timing Diagrams Control Register Information Control Register Map CONTROL REGISTER DETAILS Register 1: DSCG (Discharge Switch Control), Address 0x01 Register 2: SFTTIM1234 (Soft Start Time for Channel 1, Channel 2, Channel 3, and Channel 4), Address 0x02 Register 3: SFTTIM567 (Soft Start Time for Channel 5, Channel 6, and Channel 7), Address 0x03 Register 4: EN_DLY12 (Enable Delay Time for Channel 1 and Channel 2), Address 0x04 Register 5: EN_DLY34 (Enable Delay Time for Channel 3 and Channel 4), Address 0x05 Register 6: EN_DLY56 (Enable Delay Time for Channel 5 and Channel 6), Address 0x06 Register 7: EN_DLY7 (Enable Delay Time for Channel 7), Address 0x07 Register 8: DIS_DLY12 (Disable Delay Time for Channel 1 and Channel 2), Address 0x08 Register 9: DIS_DLY34 (Disable Delay Time for Channel 3 and Channel 4), Address 0x09 Register 10: DIS_DLY56 (Disable Delay Time for Channel 5 and Channel 6), Address 0x0A Register 11: DIS_DLY7 (Disable Delay Time for Channel 7), Address 0x0B Register 12: VID1 (Output Voltage for Channel 1), Address 0x0C Register 13: VID23 (Output Voltage for Channel 2 and Channel 3), Address 0x0D Register 14: VID45 (Output Voltage for Channel 4 and Channel 5), Address 0x0E Register 15: VID6 (Output Voltage for Channel 6), Address 0x0F Register 16: VID7_LDO12 (Output Voltage for Channel 7, LDO1, and LDO2), Address 0x10 Register 17: DVS12 (DVS Control for Channel 1 and Channel 2), Address 0x11 Register 18: SEL_FREQ (Switching Frequency for Channel 1 to Channel 6), Address 0x12 Register 19: SEL_FREQ_CP (Charge Pump Frequency), Address 0x13 Register 20: SEL_PHASE (Switching Phase for Channel 1 to Channel 6), Address 0x14 Register 23: PROT_DLY (Undervoltage/Overvoltage Protection Delay Times), Address 0x17 Register 24: PWRG (Power-Good Status), Address 0x18 Register 25: MASK_PWRG (Power-Good Masked Channels), Address 0x19 Register 26: UVPST (Undervoltage Protection Status), Address 0x1A Register 27: OVPST (Overvoltage Protection Status), Address 0x1B Register 28: AUTO-PSM (Auto PSM or Forced PWM Mode for Channel 1 to Channel 6), Address 0x1C Register 29: SEQ_MODE (Sequencer Mode), Address 0x1D Register 30: ADJ_BST_VTH6 (Adjust Boost Kick-In Threshold and Regulation Mode for Channel 6), Address 0x1E Register 31: OPT_SR_ADJ (Slew Rate Adjustment for Channel 1 to Channel 6), Address 0x1F Register 32: DCM56_GSCAL1 (Auto DCM for Channel 5 and Channel 6, Gate Scaling for Channel 1), Address 0x20 Register 33: SEL_INP_LDO12 (Input Selection for LDO1 and LDO2), Address 0x21 Register 34: SEL_IND_UV5 (Independent UVP Control for Channel 5), Address 0x22 Register 35: OPTION_SEL (Channel 1 Output Voltage Reduction, Disable Delay Time Increase, EN34 Function), Address 0x23 Register 48: PCTRL (Channel Enable Control), Address 0x30 Factory Default Options Outline Dimensions Ordering Guide