Datasheet ADP5014 (Analog Devices) - 5

Data Sheet ADP5014 Parameter Symbol Min Typ Max Unit Test Conditions/Comments
THERMAL SHUTDOWN Thermal Shutdown Threshold TSHDN 150 °C Thermal Shutdown Hysteresis THYS 15 °C
BUCK REGULATOR SPECIFICATIONS
VIN = 5 V, fSW = 1.2 MHz for all channels, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CHANNEL 1 SYNC BUCK REGULATOR Load Current ILOAD1 4 A Output Characteristics VFB1 Voltage Accuracy −40°C ≤ TJ ≤ +125°C VFB1 −0.6 +0.6 % VSET1 = VREF −1.0 +1.0 % VSET1 = ½ × VREF Feedback Bias Current IFB1 0.1 μA VSET1 Bias Current IVSET1 0.1 μA SW1 Pin High-Side Power Field Effect RDS(ON)1H 49 80 mΩ Pin to pin measurement Transistor (FET) On Resistance Low-Side Power FET RDS(ON)1L 37 60 mΩ Pin to pin measurement On Resistance Current-Limit Threshold ITH(ILIM1) 5.2 6.9 8.6 A RCFG1 = 0 kΩ 2.5 3.5 4.5 A RCFG1 = 17.8 kΩ Minimum On Time tMIN_ON1 60 90 ns fSW = 500 kHz to 2.5 MHz Minimum Off Time tMIN_OFF1 50 80 ns fSW = 500 kHz to 2.5 MHz Error Amplifier, COMP1 Pin EA Transconductance gm1 700 800 900 μS Soft Start Time tSS1 2 ms Timer ×1 option 16 ms Timer ×8 option Programmable Soft Start Range 2 16 ms Hiccup Time tHICCUP1 7 × tSS1 ms COUT Discharge Switch On RDIS1 85 Ω Resistance CHANNEL 2 SYNC BUCK REGULATOR Load Current ILOAD2 4 A Output Characteristics VFB2 Voltage Accuracy −40°C ≤ TJ ≤ +125°C VFB2 −0.6 +0.6 % VSET2 = VREF −1.0 +1.0 % VSET2 = ½ × VREF Feedback Bias Current IFB2 0.1 μA VSET2 Bias Current IVSET2 0.1 μA SW2 Pin High-Side Power FET On RDS(ON)2H 49 80 mΩ Pin to pin measurement Resistance Low-Side Power FET On RDS(ON)2L 37 60 mΩ Pin to pin measurement Resistance Current-Limit Threshold ITH(ILIM2) 5.2 6.9 8.6 A RCFG1 = 0 kΩ 2.5 3.5 4.5 A RCFG1 = 17.8 kΩ Minimum On Time tMIN_ON2 60 90 ns fSW = 500 kHz to 2.5 MHz Minimum Off Time tMIN_OFF2 50 80 ns fSW = 500 kHz to 2.5 MHz Error Amplifier, COMP2 Pin Transconductance gm2 700 800 900 μS Rev. 0 | Page 5 of 34 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode FPWM and Automatic PWM/PSM Modes LOW NOISE ARCHITECTURE INTERNAL REFERENCE (VREF) ADJUSTABLE OUTPUT VOLTAGE FUNCTION CONFIGURATIONS (CFG1 AND CFG2) PARALLEL OPERATION MANUAL/SEQUENCE MODE Manual Mode (Precision Enable) Sequence Mode GENERAL PURPOSE INPUT/OUTPUT (GPIO) OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT POWER-GOOD FUNCTION UV COMPARATOR (SEQUENCE MODE ONLY) SOFT START STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLD BACK SHORT-CIRCUIT PROTECTION (SCP) OVERVOLTAGE PROTECTION UNDERVOLTAGE LOCKOUT ACTIVE OUTPUT DISCHARGE SWITCH THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL PROGRAMMING THE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLES SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CONFIGUATIONS (CFG1 AND CFG2) SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR DESIGNING THE COMPENSATION NETWORK PCB LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY PROGRAMMABLE OPTIONS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE