Datasheet ADP5003 (Analog Devices) - 4

ADP5003 Data Sheet BUCK REGULATOR SPECIFICATIONS
VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
OUTPUT CHARACTERISTICS Programmable Output Voltage Range1 VVOUT1 0.6 5.0 V Buck Regulator Gain ABUCK 2.5 Error Amplifier Transconductance gm1 509 600 661 µS Buck Output Voltage Accuracy2 σVOUT1 −1 +1 % Load 1 current (ILOAD1) = 10 mA Regulation Line (ΔVVOUT1/VVOUT1)/ΔVPVIN1 0.004 %/V ILOAD1 = 10 mA Load (ΔVVOUT1/VVOUT1)/ΔIVOUT1 0.04 %/A 0 mA ≤ ILOAD1 ≤ 3 A, VPVIN1 = 12 V Total Output Voltage Accuracy σBUCK ±1.5 % 4.2 V ≤ VPVIN1 ≤ 15 V, 1 mA ≤ ILOAD1 ≤ 3 A OPERATING SUPPLY CURRENT IIN 3.8 mA ILOAD1 = 0 mA, LDO disabled SW1 CHARACTERISTICS SW1 On Resistance RPFET 130 200 mΩ VPVIN1 = 15 V (PVIN1 to SW1) RNFET 60 100 mΩ VPVIN1 = 15 V (SW1 to PGND1) Current Limit 1 ILIMIT1 3.5 A Negative channel field effect transistor (NFET) switch valley current limit −1 A Negative current limit Slew Rate SLEWSW1 1.6 V/ns VPVIN1 = 15 V, IVOUT1 = 1 A Minimum On Time3 tMIN_ON 35 ns Minimum Off Time tMIN_OFF 100 128 ns BUCK REGULATOR ACTIVE PULL DOWN RPDWN-B 90 Ω Channel disabled BUCK REGULATOR SOFT START (SS) tSSBUCK 2 ms HICCUP TIME tHICCUP 33 ms VSETx ADJUSTABLE INPUT BIAS CURRENT IVSET1, IVSET2 10 150 nA 4.2 V ≤ VPVINSYS ≤ 15 V OSCILLATOR Internal Switching Frequency 1 fSW1 2.25 2.5 2.75 MHz RT current (IRT) = 10 µA Internal Switching Frequency 2 fSW2 0.26 0.3 0.34 MHz IRT = 1 µA SYNC Frequency Range fSYNC 0.3 2.5 MHz Minimum Pulse Width Positive 20 ns Negative 10 ns 1 The switching frequency, minimum on time, and minimum off time dictates the output voltage range. 2 The buck output voltage accuracy is relative to the nominal output voltage and accounts for reference voltage, gain, and offset error. 3 The minimum on time indicates the minimum turn on time to ensure fixed frequency switching. Rev. 0 | Page 4 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO SPECIFICATIONS ADAPTIVE HEADROOM CONTROLLER SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Adaptive Headroom Control Precision Enable/Shutdown Undervoltage Lockout (UVLO) Thermal Shutdown (TSD) Active Pull Down Soft Start (SS) Power-Good BUCK REGULATOR Control Scheme Oscillator Frequency Control External Oscillator Synchronization Buck Startup Current-Limit and Short-Circuit Protection LDO REGULATOR LDO Startup Current Limit Differential Remote Sensing POWER-GOOD OUTPUT VOLTAGE OF THE BUCK REGULATOR OUTPUT VOLTAGE OF THE LDO REGULATOR VOLTAGE CONVERSION LIMITATIONS COMPONENT SELECTION Output Capacitors Input Capacitor Inductor COMPENSATION COMPONENTS DESIGN JUNCTION TEMPERATURE BUCK REGULATOR DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY FOR THE BUCK REGULATOR SETTING THE OUTPUT VOLTAGE FOR THE BUCK REGULATOR SELECTING THE INDUCTOR FOR THE BUCK REGULATOR SELECTING THE OUTPUT CAPACITOR FOR THE BUCK REGULATOR DESIGNING THE COMPENSATION NETWORK FOR THE BUCK REGULATOR SELECTING THE INPUT CAPACITOR FOR THE BUCK REGULATOR ADAPTIVE HEADROOM CONTROL DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY FOR THE BUCK REGULATOR USING ADAPTIVE HEADROOM CONTROL SETTING THE OUTPUT VOLTAGE FOR THE BUCK REGULATOR USING ADAPTIVE HEADROOM CONTROL SELECTING THE INDUCTOR FOR THE BUCK REGULATOR USING ADAPTIVE HEADROOM CONTROL SELECTING THE OUTPUT CAPACITORS FOR THE BUCK REGULATOR USING ADAPTIVE HEADROOM CONTROL SELECTING THE INPUT CAPACITOR FOR THE BUCK REGULATOR USING ADAPTIVE HEADROOM CONTROL RECOMMENDED BUCK EXTERNAL COMPONENTS FOR THE BUCK REGULATOR BUCK CONFIGURATIONS INDEPENDENT ADAPTIVE HEADROOM LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE