Datasheet LT1352, LT1353 (Analog Devices) - 10

LT1352/LT1353
U U W U APPLICATIONS INFORMATION
applications where DC accuracy must be maximized. The input step. The graph Slew Rate vs Input Level illustrates inputs can withstand transient differential input voltages this relationship. In higher gain configurations the large- up to 10V without damage and need no clamping or source signal performance and the small-signal performance resistance for protection. Differential inputs, however, both look like a single pole response. generate large supply currents (tens of mA) as required for Capacitive load compensation is provided by the R high slew rates. If the device is used with sustained C, CC network which is bootstrapped across the output stage. differential inputs, the average supply current will in- When the amplifier is driving a light load the network has crease, excessive power dissipation will result and the part no effect. When driving a capacitive load (or a low value may be damaged.
The part should not be used as a
resistive load) the network is incompletely bootstrapped
comparator, peak detector or other open-loop applica-
and adds to the compensation at the high impedance
tion with large, sustained differential inputs
. Under node. The added capacitance slows down the amplifier normal, closed-loop operation, an increase of power dis- and a zero is created by the RC combination, both of which sipation is only noticeable in applications with large slewing improve the phase margin. The design ensures that even outputs and is proportional to the magnitude of the for very large load capacitances, the total phase lag can differential input voltage and the percent of time that the never exceed 180 degrees (zero phase margin) and the inputs are apart. Measure the average supply current for amplifier remains stable. the application in order to calculate the power dissipation.
Power Dissipation Circuit Operation
The LT1352/LT1353 combine high speed and large output The LT1352/LT1353 circuit topology is a true voltage drive in small packages. Because of the wide supply feedback amplifier that has the slewing behavior of a voltage range, it is possible to exceed the maximum current feedback amplifier. The operation of the circuit can junction temperature of 150°C under certain conditions. be understood by referring to the Simplified Schematic. Maximum junction temperature TJ is calculated from the The inputs are buffered by complementary NPN and PNP ambient temperature TA and power dissipation PD as emitter followers which drive R1, a 1k resistor. The input follows: voltage appears across the resistor generating currents LT1352CN8: T which are mirrored into the high impedance node and J = TA + (PD)(130°C/W) LT1352CS8: T compensation capacitor C J = TA + (PD)(190°C/W) T. Complementary followers LT1353CS: T form an output stage which buffers the gain node from the J = TA + (PD)(150°C/W) load. The output devices Q19 and Q22 are connected to Worst-case power dissipation occurs at the maximum form a composite PNP and a composite NPN. supply current and when the output voltage is at 1/2 of either supply voltage (or the maximum swing if less than The bandwidth is set by the input resistor and the capaci- 1/2 supply voltage). For each amplifier P tance on the high impedance node. The slew rate is D(MAX) is: determined by the current available to charge the high PD(MAX) = (V+ – V–)(IS(MAX)) + (V+/2)2/RL or impedance node capacitance. This current is the differen- (V+ – V –)(IS(MAX)) + (V+ – VMAX)(IMAX) tial input voltage divided by R1, so the slew rate is Example: LT1353 in S14 at 85°C, VS = ±15V, RL = 500Ω, proportional to the input. Highest slew rates are therefore VOUT = ±5V (±10mA) seen in the lowest gain configurations. For example, a 10V output step in a gain of 10 has only a 1V input step whereas PD(MAX) = (30V)(380µA) + (15V – 5V)(10mA) = 111mW the same output step in unity gain has a 10 times greater TJ = 85°C + (4)(111mW)(150°C/W) = 152°C 13523fa 10