Datasheet LT1792 (Analog Devices) - 9

LT1792
O U U W U APPLICATI S I FOR ATIO
the input of the LT1792. The charge across the transducer expense of reduced dynamic range. To illustrate this capacitance, CS, is transferred to the feedback capacitor benefit, let’s take the following example: CF, resulting in a change in voltage, dV, equal to dQ/CF. An LT1792CS8 operates at an ambient temperature of The gain therefore is CF/CS. For unity gain, the CF should 25°C with ±15V supplies, dissipating 159mW of power equal the transducer capacitance plus the input capaci- (typical supply current = 5.3mA). The SO-8 package has a tance of the LT1792 and RF should equal RS. In the θ noninverting mode example, the transducer current is JA of 190°C/W, which results in a die temperature in- crease of 30.2°C or a room temperature die operating converted to a change in voltage by the transducer capaci- temperature of 55.2°C. At ±5V supplies, the die tempera- tance; this voltage is then buffered by the LT1792 with a ture increases by only one third of the previous amount or gain of 1 + R1/R2. A DC path is provided by RS, which is 10.1°C resulting in a typical die operating temperature of either the transducer impedance or an external resistor. only 35.1°C. A 20 degree reduction of die temperature is Since RS is usually several orders of magnitude greater achieved at the expense of a 20V reduction in dynamic than the parallel combination of R1 and R2, RB is added to range. balance the DC offset caused by the noninverting input bias current and R To take full advantage of a wide input common mode S. The input bias currents, although small at room temperature, can create significant errors at range, the LT1792 was designed to eliminate phase rever- higher temperature, especially with transducer resistances sal. Referring to the photographs shown in Figure 4, the of up to 100M or more. The optimum value for R LT1792 is shown operating in the follower mode (A S is V = 1) determined by equating the thermal noise (4kTR at ±5V supplies with the input swinging ±5.2V. The output S) to the current noise times R of the LT1792 clips cleanly and recovers with no phase S, [(2qIB) • RS], resulting in R reversal. This has the benefit of preventing lock-up in B = 2VT/IB (VT = 26mV at 25°C). A parallel capacitor, CB, is used to cancel the phase shift caused by the op amp servo systems and minimizing distortion components. input capacitance and RB.
High Speed Operation Reduced Power Supply Operation
The low noise performance of the LT1792 was achieved The LT1792 can be operated from ±5V supplies for lower by making the input JFET differential pair large to maxi- power dissipation resulting in lower I mize the first stage gain. Increasing the JFET geometry B and noise at the
INPUT:
±
5.2V Sine Wave LT1792 Output
1792 F04a 1792 F03b
Figure 4. Voltage Follower with Input Exceeding the Common Mode Range ( VS =
±
5V)
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