Datasheet LT1190 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | Ultrahigh Speed Operational Amplifier |
| Páginas / Página | 12 / 8 — APPLICATIO S I FOR ATIO Power Supply Bypassing. No Supply Bypass … |
| Formato / tamaño de archivo | PDF / 268 Kb |
| Idioma del documento | Inglés |
APPLICATIO S I FOR ATIO Power Supply Bypassing. No Supply Bypass Capacitors. Settling Time Poor Bypass
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LT1190
U U W U APPLICATIO S I FOR ATIO Power Supply Bypassing
In most applications, and those requiring good settling time, it is important to use multiple bypass capacitors. A The LT1190 is quite tolerant of power supply bypassing. 0.1µF ceramic disc in parallel with a 4.7µF tantalum is In some applications a 0.1µF ceramic disc capacitor recommended. Two oscilloscope photos with different placed 1/2 inch from the amplifier is all that is required. A bypass conditions are used to illustrate the settling time scope photo of the amplifier output with no supply characteristics of the amplifier. Note that although the bypassing is used to demonstrate this bypassing toler- output waveform looks acceptable at 1V/DIV, when ampli- ance, RL = 1kΩ. fied to 1mV/DIV the settling time to 2mV is 4.244µs for the 0.1µF bypass; the time drops to 163ns with multiple
No Supply Bypass Capacitors
bypass capacitors.
Settling Time Poor Bypass
V V OUT OUT 0V 1V/DIV 1mV/DIV LT1190 • TA04 AV = –1, IN DEMO BOARD, RL = 1kΩ Supply bypassing can also affect the response in the LT1190 • TA06 frequency domain. It is possible to see a slight 1dB rise in SETTLING TIME TO 2mV, AV = –1 SUPPLY BYPASS CAPACITORS = 0.1µF the frequency response at 130MHz depending on the gain configuration, supply bypass, inductance in the supply
Settling Time Good Bypass
leads and printed circuit board layout. This can be further minimized by not using a socket.
Closed-Loop Voltage Gain vs Frequency
20 VS = ±5V V V OUT OUT T 0V A = 25°C 1V/DIV 1mV/DIV RL = 1k 10 AV = 2 AV = 1 0 LT1190 • TA07 SETTLING TIME TO 2mV, AV = –1 –10 SUPPLY BYPASS CAPACITORS = 0.1µF + 4.7µF TANTALUM CLOSED-LOOP VOLTAGE GAIN (dB) –20 100k 1M 10M 100M 1G FREQUENCY (Hz) LT1190 • TA05 8
U U W U APPLICATIO S I FOR ATIO Power Supply Bypassing
In most applications, and those requiring good settling time, it is important to use multiple bypass capacitors. A The LT1190 is quite tolerant of power supply bypassing. 0.1µF ceramic disc in parallel with a 4.7µF tantalum is In some applications a 0.1µF ceramic disc capacitor recommended. Two oscilloscope photos with different placed 1/2 inch from the amplifier is all that is required. A bypass conditions are used to illustrate the settling time scope photo of the amplifier output with no supply characteristics of the amplifier. Note that although the bypassing is used to demonstrate this bypassing toler- output waveform looks acceptable at 1V/DIV, when ampli- ance, RL = 1kΩ. fied to 1mV/DIV the settling time to 2mV is 4.244µs for the 0.1µF bypass; the time drops to 163ns with multiple
No Supply Bypass Capacitors
bypass capacitors.
Settling Time Poor Bypass
V V OUT OUT 0V 1V/DIV 1mV/DIV LT1190 • TA04 AV = –1, IN DEMO BOARD, RL = 1kΩ Supply bypassing can also affect the response in the LT1190 • TA06 frequency domain. It is possible to see a slight 1dB rise in SETTLING TIME TO 2mV, AV = –1 SUPPLY BYPASS CAPACITORS = 0.1µF the frequency response at 130MHz depending on the gain configuration, supply bypass, inductance in the supply
Settling Time Good Bypass
leads and printed circuit board layout. This can be further minimized by not using a socket.
Closed-Loop Voltage Gain vs Frequency
20 VS = ±5V V V OUT OUT T 0V A = 25°C 1V/DIV 1mV/DIV RL = 1k 10 AV = 2 AV = 1 0 LT1190 • TA07 SETTLING TIME TO 2mV, AV = –1 –10 SUPPLY BYPASS CAPACITORS = 0.1µF + 4.7µF TANTALUM CLOSED-LOOP VOLTAGE GAIN (dB) –20 100k 1M 10M 100M 1G FREQUENCY (Hz) LT1190 • TA05 8