Datasheet LT1363 (Analog Devices) - 10

LT1363
U U W U APPLICATIONS INFORMATION Input Considerations
temperature under certain conditions. Maximum junction temperature (T Each of the LT1363 inputs is the base of an NPN and a PNP J) is calculated from the ambient tempera- ture (T transistor whose base currents are of opposite polarity A) and power dissipation (PD) as follows: and provide first-order bias current cancellation. Because LT1363CN8: T of variation in the matching of NPN and PNP beta, the J = TA + (PD x 130°C/W) polarity of the input bias current can be positive or nega- LT1363CS8: TJ = TA + (PD x 190°C/W) tive. The offset current does not depend on NPN/PNP beta matching and is well controlled. The use of balanced Worst case power dissipation occurs at the maximum source resistance at each input is recommended for supply current and when the output voltage is at 1/2 of applications where DC accuracy must be maximized. either supply voltage (or the maximum swing if less than 1/2 supply voltage). Therefore PDMAX is: The inputs can withstand transient differential input volt- ages up to 10V without damage and need no clamping or PDMAX = (V+ – V–)(ISMAX) + (V+/2)2/RL source resistance for protection. Differential inputs, how- ever, generate large supply currents (tens of mA) as Example: LT1363CS8 at 70°C, VS = ±15V, RL = 390Ω required for high slew rates. If the device is used with sustained differential inputs, the average supply current PDMAX = (30V)(8.7mA) + (7.5V)2/390Ω = 405mW will increase, excessive power dissipation will result and the part may be damaged.
The part should not be used as
TJMAX = 70°C + (405mW)(190°C/W) = 147°C
a comparator, peak detector or other open-loop applica- tion with large, sustained differential inputs
. Under
Circuit Operation
normal, closed-loop operation, an increase of power dis- The LT1363 circuit topology is a true voltage feedback sipation is only noticeable in applications with large slewing amplifier that has the slewing behavior of a current feed- outputs and is proportional to the magnitude of the back amplifier. The operation of the circuit can be under- differential input voltage and the percent of the time that stood by referring to the simplified schematic. The inputs the inputs are apart. Measure the average supply current are buffered by complementary NPN and PNP emitter for the application in order to calculate the power dissipa- followers which drive a 500Ω resistor. The input voltage tion. appears across the resistor generating currents which are
Single Supply Operation
mirrored into the high impedance node. Complementary followers form an output stage which buffers the gain The LT1363 is specified at ±15V, ±5V, and ±2.5V supplies, node from the load. The bandwidth is set by the input but it is also well suited to single supply operation down resistor and the capacitance on the high impedance node. to a single 5V supply. The symmetrical input Ccmmon The slew rate is determined by the current available to mode range and output swing make the device well suited charge the gain node capacitance. This current is the for applications with a single supply if the the input and differential input voltage divided by R1, so the slew rate is output swing ranges are centered (i.e., a DC bias of 2.5V proportional to the input. Highest slew rates are therefore on the input and the output). For 5V video applications seen in the lowest gain configurations. For example, a 10V with an assymetrical swing, an offset of 2V on the input output step in a gain of 10 has only a 1V input step, works best. whereas the same output step in unity gain has a 10 times greater input step. The curve of Slew Rate vs Input Level
Power Dissipation
illustrates this relationship. The LT1363 is tested for slew The LT1363 combines high speed and large output drive rate in a gain of –2 so higher slew rates can be expected in a small package. Because of the wide supply voltage in gains of 1 and –1, and lower slew rates in higher gain range, it is possible to exceed the maximum junction configurations. 10