Datasheet LT1203, LT1205 (Analog Devices) - 7

LT1203/LT1205
W U TYPICAL PERFOR A CE CHARACTERISTICS Channel 1 Enable Channel 1 Disable
EN EN (PIN 6) (PIN 6) VOUT VOUT (PIN 7) (PIN 7) V LT1203/05 • TPC19 LT1203/05 • TPC20 S = ±15V VINO = 1V VS = ±15V VINO = 1V RL = 1k VIN1 = 0V RL = 1k VIN1 = 0V
O U U W U APPLICATI S I FOR ATIO Input Protection
with ground plane to ensure high channel separation. For minimum peaking, maximum bandwidth and maximum The logic inputs have ESD protection (≥ 2kV) and short- gain flatness sockets are not recommended because they ing them to 12V or 15V will cause excessive current to can add considerable stray inductance and capacitance. If flow. Limit the current to less than 50mA when driving a socket must be used, use a low profile, low capacitance the logic above 6V. The analog inputs are protected socket such as the SamTec ISO-308. against ESD and overvoltage with internal SCRs. For inputs ≥±2.8V the SCRs will fire and the DC current
Switching Transients
should be limited to 20mA. The LT1203/LT1205 use input buffers to ensure switching
Power Supplies
transients do not couple to other video equipment sharing the input line. Output switching transients are about The LT1203/LT1205 will operate from ±5V (10V total) to ± 50mV 15V (30V total) and is specified over this range. Charac- P-P with a 20ns duration and input transients are teristics change very little over this voltage range. It is not
LT1203 Channel-to-Channel Switching Transient
necessary to use equal value supplies however, the output offset voltage will change. The offset will change about 300µV per volt of supply mismatch. The LT1203/LT1205 have a very wide bandwidth yet are tolerant of power OUTPUT 50mV/DIV supply bypassing. The power supplies should be by- passed with a 0.1µF or 0.01µF ceramic capacitor within 0.5 INPUT inch of the part. 20mV/DIV
Circuit Layout
LOGIC Use a ground plane to ensure a low impedance ground is (PIN 5) available throughout the PCB layout. Separate the inputs RS = 50Ω LT1203/05 • AI01 7