Datasheet LT1208, LT1209 (Analog Devices) - 6

LT1208/LT1209
W U TYPICAL PERFOR A CE CHAR C A TERISTICS Gain-Bandwidth and Phase Margin Total Harmonic Distortion vs Supply Voltage Slew Rate vs Supply Voltage vs Frequency
60 62 600 0.01 TA = 25°C TA = 25°C TA = 25°C 55 60 A VOUT = 3VRMS PHASE MARGIN V = –1 500 RL = 500Ω 50 58 PHASE MARGIN (DEG) µs) 45 56 –SR +SR 400 40 54 35 52 300 SLEW RATE (V/ GAIN-BANDWIDTH (MHz) 30 50 AV = –1 GAIN BANDWIDTH 200 25 48 TOTAL HARMONIC DISTORTION (%) AV = 1 20 46 100 0.001 0 5 10 15 20 0 5 10 15 20 10 100 1k 10k 100k SUPPLY VOLTAGE (±V) SUPPLY VOLTAGE (±V) FREQUENCY (Hz) 1208/09 G19 1208/09 G21 1208/09 G20
O U U W U APPLICATI S I FOR ATIO Layout and Passive Components Capacitive Loading
As with any high speed operational amplifier, care must be The LT1208/LT1209 amplifiers are stable with capacitive taken in board layout in order to obtain maximum perfor- loads. This is accomplished by sensing the load induced mance. Key layout issues include: use of a ground plane, output pole and adding compensation at the amplifier gain minimization of stray capacitance at the input pins, short node. As the capacitive load increases, both the bandwidth lead lengths, RF-quality bypass capacitors located close and phase margin decrease so there will be peaking in the to the device (typically 0.01µF to 0.1µF), and use of low frequency domain and in the transient response. The ESR bypass capacitors for high drive current applications photo of the small-signal response with 1000pF load (typically 1µF to 10µF tantalum). Sockets should be shows 50% peaking. The large-signal response with a avoided when maximum frequency performance is re- 10,000pF load shows the output slew rate being limited by quired, although low profile sockets can provide reason- the short-circuit current. To reduce peaking with capaci- able performance up to 50MHz. For more details see tive loads, insert a small decoupling resistor between the Design Note 50. The parallel combination of the feedback output and the load, and add a capacitor between the resistor and gain setting resistor on the inverting input output and inverting input to provide an AC feedback path. combine with the input capacitance to form a pole which Coaxial cable can be driven directly, but for best pulse can cause peaking. If feedback resistors greater than 5k fidelity the cable should be doubly terminated with a are used, a parallel capacitor of value resistor in series with the output. CF ≥ RG × CIN/RF should be used to cancel the input pole and optimize dynamic performance. For unity-gain applications where a large feedback resistor is used, CF should be greater than or equal to CIN. 6