Datasheet AD8369 (Analog Devices)

45 dB Digitally Controlled VGA LF to 600 MHz AD8369 FEATURES FUNCTIONAL BLOCK DIAGRAM Digitally Controlled Variable Gain in 3 dB Steps BIT3 BIT2 BIT1 BIT0 –5 dB to +40 dB (RL = 1 k
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) –10 dB to +35 dB (RL = 200
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) VPOS Less than 0.2 dB Flatness over a +20 MHz Bandwidth BIAS DENB 3dB STEP GAIN CODE DECODE PWUP up to 380 MHz SENB 4-Bit Parallel or 3-Wire Serial Interface FILT Differential 200
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Input and Output Impedance OPHI Single 3.0 V–5.5 V Supply Gm CELLS Draws 37 mA at 5 V OPLO Power-Down <1 mA Maximum APPLICATIONS INHI Cellular/PCS Base Stations IF Sampling Receivers CMDC Fixed Wireless Access INLO Wireline Modems COMM Instrumentation COMM PRODUCT DESCRIPTION
OPHI and OPLO. The overall gain depends upon the source The AD8369 is a high performance digitally controlled variable and load impedances due to the resistive nature of the input and gain amplifier (VGA) for use from low frequencies to a –3 dB output ports. frequency of 600 MHz at all gain codes. The AD8369 delivers Digital control of the AD8369 is achieved using either a serial or excellent distortion performance: the two-tone, third-order a parallel interface. The mode of digital control is selected by intermodulation distortion is –69 dBc at 70 MHz for a 1 V p-p connecting a single pin (SENB) to ground or the positive sup- composite output into a 1 kW load. The AD8369 has a nominal ply. Digital control pins can be driven with standard CMOS noise figure of 7 dB when at maximum gain, then increases with logic levels. decreasing gain. Output IP3 is +19.5 dBm at 70 MHz into a The AD8369 may be powered on or off by a logic level applied 1 kW load and remains fairly constant over the gain range. to the PWUP pin. For a logic high, the chip powers up rapidly The signal input is applied to pins INHI and INLO. Variable gain to its nominal quiescent current of 37 mA at 25ºC. When low, is achieved via two methods. The 6dB gain steps are implemented the total dissipation drops to less than a few milliwatts. using a discrete X-AMP® structure, in which the input signal is The AD8369 is fabricated on an Analog Devices proprietary, high progressively attenuated by a 200W R-2R ladder network that performance 25 GHz silicon bipolar IC process and is available also sets the input impedance; the 3dB steps are implemented at in a 16-lead TSSOP package for the industrial temperature range the output of the amplifier. This combination provides very of –40 accurate 3dB gain steps over a span of 45 dB. The output imped- rC to +85rC. A populated evaluation board is available. ance is set by on-chip resistors across the differential output pins,
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Document Outline Features Applications Functional Block Diagram Product Description Specifications Timing Specifications Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Theroy of Operation Input Attentuator and Output 3 dB Step Fixed Gain Amplifier Input and Output Interfaces Noise and Distortion Offset Control Loop Digital Control Basic Connections Input-Output Interface Reducing Gain Sensitivity to Input and Output Impedance Variation Operation from a Single-Sided Source Interfacing to an ADC PCB Layout Considerations Evaluation Board Evaluation Board Software Appendix Characterization Equipment Definitions of Selected Parameters Composite Waveform Assumption Outline Dimensions Ordering Guide Revision History