Datasheet AD8351 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | Low Distortion Differential RF/IF Amplifier |
| Páginas / Página | 19 / 6 — AD8351. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. PWUP 1. … |
| Revisión | D |
| Formato / tamaño de archivo | PDF / 484 Kb |
| Idioma del documento | Inglés |
AD8351. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. PWUP 1. 10 VOCM. PWU. RGP1 2. 9 VPOS. INHI. 8 OPHI. TOP VIEW. INLO
Línea de modelo para esta hoja de datos
Versión de texto del documento
AD8351 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS P M PWUP 1 10 VOCM C PWU NC NC VO RGP1 2 9 VPOS AD8351 61 5 4 3 INHI 1 1 1 3 8 OPHI TOP VIEW INLO (Not to Scale) 4 7 OPLO
50 -0
RGP2 5 6 COMM RGP1 1 12 VPOS
45 1 3 0
INHI 2 AD8351 11 OPHI TOP VIEW INLO 3 10 OPLO (Not to Scale) RGP2 4 9 COMM 5 6 7 8 NC NC NC NC NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2
2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO
00
GND AND MUST BE SOLDERED TO A LOW IMPEDANCE GROUND PLANE.
03145- Figure 2. 10-Lead MSOP Pin Configuration Figure 3. 16-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions Pin No. 10-Lead MSOP 16-Lead LFCSP Mnemonic Description
1 16 PWUP Apply a positive voltage (1.3 V ≤ VPWUP ≤ VPOS) to activate device. 2 1 RGP1 Gain Resistor Input 1. 3 2 INHI Balanced Differential Input. Biased to midsupply, typically ac-coupled. 4 3 INLO Balanced Differential Input. Biased to midsupply, typically ac-coupled. 5 4 RGP2 Gain Resistor Input 2. 6 9 COMM Device Common. Connect to low impedance ground. 7 10 OPLO Balanced Differential Output. Biased to VOCM, typically ac-coupled. 8 11 OPHI Balanced Differential Output. Biased to VOCM, typically ac-coupled. 9 12 VPOS Positive Supply Voltage. 3 V to 5.5 V. 10 13 VOCM Voltage applied to this pin sets the common-mode voltage at both the input and output. Typically decoupled to ground with a 0.1 μF capacitor. 5, 6, 7, 8, 14, 15 NC No connect. Do not connect to this pin. EPAD Exposed Pad. The exposed pad is internally connected to GND and must be soldered to a low impedance ground plane. Rev. D | Page 6 of 19 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC CONCEPTS GAIN ADJUSTMENT COMMON-MODE ADJUSTMENT INPUT AND OUTPUT MATCHING SINGLE-ENDED-TO-DIFFERENTIAL OPERATION ADC DRIVING ANALOG MULTIPLEXING I/O CAPACITIVE LOADING TRANSMISSION LINE EFFECTS CHARACTERIZATION SETUP EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
50 -0
RGP2 5 6 COMM RGP1 1 12 VPOS
45 1 3 0
INHI 2 AD8351 11 OPHI TOP VIEW INLO 3 10 OPLO (Not to Scale) RGP2 4 9 COMM 5 6 7 8 NC NC NC NC NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2
2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO
00
GND AND MUST BE SOLDERED TO A LOW IMPEDANCE GROUND PLANE.
03145- Figure 2. 10-Lead MSOP Pin Configuration Figure 3. 16-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions Pin No. 10-Lead MSOP 16-Lead LFCSP Mnemonic Description
1 16 PWUP Apply a positive voltage (1.3 V ≤ VPWUP ≤ VPOS) to activate device. 2 1 RGP1 Gain Resistor Input 1. 3 2 INHI Balanced Differential Input. Biased to midsupply, typically ac-coupled. 4 3 INLO Balanced Differential Input. Biased to midsupply, typically ac-coupled. 5 4 RGP2 Gain Resistor Input 2. 6 9 COMM Device Common. Connect to low impedance ground. 7 10 OPLO Balanced Differential Output. Biased to VOCM, typically ac-coupled. 8 11 OPHI Balanced Differential Output. Biased to VOCM, typically ac-coupled. 9 12 VPOS Positive Supply Voltage. 3 V to 5.5 V. 10 13 VOCM Voltage applied to this pin sets the common-mode voltage at both the input and output. Typically decoupled to ground with a 0.1 μF capacitor. 5, 6, 7, 8, 14, 15 NC No connect. Do not connect to this pin. EPAD Exposed Pad. The exposed pad is internally connected to GND and must be soldered to a low impedance ground plane. Rev. D | Page 6 of 19 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC CONCEPTS GAIN ADJUSTMENT COMMON-MODE ADJUSTMENT INPUT AND OUTPUT MATCHING SINGLE-ENDED-TO-DIFFERENTIAL OPERATION ADC DRIVING ANALOG MULTIPLEXING I/O CAPACITIVE LOADING TRANSMISSION LINE EFFECTS CHARACTERIZATION SETUP EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE