Datasheet LT6402-20 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 300MHz Low Distortion, Low Noise Differential Amplifier/ADC Driver (AV = 20dB) |
| Páginas / Página | 16 / 9 — PI FU CTIO S. VOCM (Pin 2):. +OUTFILTERED, –OUTFILTERED (Pins 6, 7):. … |
| Formato / tamaño de archivo | PDF / 338 Kb |
| Idioma del documento | Inglés |
PI FU CTIO S. VOCM (Pin 2):. +OUTFILTERED, –OUTFILTERED (Pins 6, 7):. CCA, VCCB, VCCC (Pins 3, 10, 1):. E (Pin 11):
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LT6402-20
U U U PI FU CTIO S VOCM (Pin 2):
This pin sets the output common mode
+OUTFILTERED, –OUTFILTERED (Pins 6, 7):
Filtered voltage. Without additional biasing, both inputs bias to Outputs. These pins add a series 50Ω resistor from the this voltage as well. This input is high impedance. unfi ltered outputs and three 14pF capacitors. Each output has 14pF to V
V
EE, plus an additional 14pF between each pin
CCA, VCCB, VCCC (Pins 3, 10, 1):
Positive Power Supply (See the Block Diagram). This fi lter has a –3dB bandwidth (Normally Tied to 5V). All three pins must be tied to the of 75MHz. same voltage. Bypass each pin with 1000pF and 0.1µF capacitors as close to the package as possible. Split ⎯
E
⎯
N
⎯
A
⎯
B
⎯
L
⎯
E (Pin 11):
This pin is a TTL logic input referenced supplies are possible as long as the voltage between VCC to the VEEC pin. If low, the LT6402 is enabled and draws and VEE is 5V. typically 30mA of supply current. If high, the LT6402 is disabled and draws typically 250µA.
VEEA, VEEB, VEEC (Pins 4, 9, 12):
Negative Power Supply (Normally Tied to Ground). All three pins must be tied to
+INA, +INB (Pins 15, 16):
Positive Inputs. These pins are the same voltage. Split supplies are possible as long as normally tied together. These inputs may be DC- or AC- the voltage between VCC and VEE is 5V. If these pins are coupled. If the inputs are AC-coupled, they will self-bias not tied to ground, bypass each pin with 1000pF and 0.1µF to the voltage applied to the VOCM pin. capacitors as close to the package as possible.
–INA, –INB (Pins 14, 13):
Negative Inputs. These pins are
+OUT, –OUT (Pins 5, 8):
Outputs (Unfi ltered). These normally tied together. These inputs may be DC- or AC- pins are high bandwidth, low-impedance outputs. The DC coupled. If the inputs are AC-coupled, they will self-bias output voltage at these pins is set to the voltage applied to the voltage applied to the VOCM pin. at VOCM.
Exposed Pad (Pin 17):
Tie the pad to VEEC (Pin 12). If split supplies are used, DO NOT tie the pad to ground.
W BLOCK DIAGRA
500Ω VEEA –INA VCCA 100 14pF Ω 14 – +OUT A 5 –INB 100Ω +OUTFILTERED 13 + 50Ω 6 VEEA 500Ω VCCC VOCM + 2 C 14pF – VEEC 500Ω 50Ω –OUTFILTERED +INA VCCB 100Ω 7 16 + –OUT B 8 +INB 100Ω 15 – 14pF VEEB VEEB 500Ω BIAS 6402 BD 3 10 1 11 4 9 12 VCCA VCCB VCCC ENABLE V V V EEA EEB EEC 640220fa 9
U U U PI FU CTIO S VOCM (Pin 2):
This pin sets the output common mode
+OUTFILTERED, –OUTFILTERED (Pins 6, 7):
Filtered voltage. Without additional biasing, both inputs bias to Outputs. These pins add a series 50Ω resistor from the this voltage as well. This input is high impedance. unfi ltered outputs and three 14pF capacitors. Each output has 14pF to V
V
EE, plus an additional 14pF between each pin
CCA, VCCB, VCCC (Pins 3, 10, 1):
Positive Power Supply (See the Block Diagram). This fi lter has a –3dB bandwidth (Normally Tied to 5V). All three pins must be tied to the of 75MHz. same voltage. Bypass each pin with 1000pF and 0.1µF capacitors as close to the package as possible. Split ⎯
E
⎯
N
⎯
A
⎯
B
⎯
L
⎯
E (Pin 11):
This pin is a TTL logic input referenced supplies are possible as long as the voltage between VCC to the VEEC pin. If low, the LT6402 is enabled and draws and VEE is 5V. typically 30mA of supply current. If high, the LT6402 is disabled and draws typically 250µA.
VEEA, VEEB, VEEC (Pins 4, 9, 12):
Negative Power Supply (Normally Tied to Ground). All three pins must be tied to
+INA, +INB (Pins 15, 16):
Positive Inputs. These pins are the same voltage. Split supplies are possible as long as normally tied together. These inputs may be DC- or AC- the voltage between VCC and VEE is 5V. If these pins are coupled. If the inputs are AC-coupled, they will self-bias not tied to ground, bypass each pin with 1000pF and 0.1µF to the voltage applied to the VOCM pin. capacitors as close to the package as possible.
–INA, –INB (Pins 14, 13):
Negative Inputs. These pins are
+OUT, –OUT (Pins 5, 8):
Outputs (Unfi ltered). These normally tied together. These inputs may be DC- or AC- pins are high bandwidth, low-impedance outputs. The DC coupled. If the inputs are AC-coupled, they will self-bias output voltage at these pins is set to the voltage applied to the voltage applied to the VOCM pin. at VOCM.
Exposed Pad (Pin 17):
Tie the pad to VEEC (Pin 12). If split supplies are used, DO NOT tie the pad to ground.
W BLOCK DIAGRA
500Ω VEEA –INA VCCA 100 14pF Ω 14 – +OUT A 5 –INB 100Ω +OUTFILTERED 13 + 50Ω 6 VEEA 500Ω VCCC VOCM + 2 C 14pF – VEEC 500Ω 50Ω –OUTFILTERED +INA VCCB 100Ω 7 16 + –OUT B 8 +INB 100Ω 15 – 14pF VEEB VEEB 500Ω BIAS 6402 BD 3 10 1 11 4 9 12 VCCA VCCB VCCC ENABLE V V V EEA EEB EEC 640220fa 9