Datasheet AD8352 (Analog Devices) - 3
| Fabricante | Analog Devices |
| Descripción | 2 GHz Ultralow Distortion Differential RF/IF Amplifier |
| Páginas / Página | 19 / 3 — Data Sheet. AD8352. SPECIFICATIONS. Table 1. Parameter. Conditions. Min. … |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 464 Kb |
| Idioma del documento | Inglés |
Data Sheet. AD8352. SPECIFICATIONS. Table 1. Parameter. Conditions. Min. Typ. Max. Unit
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Data Sheet AD8352 SPECIFICATIONS
VS = 5 V, RL = 200 Ω differential, RG = 118 Ω (AV = 10 dB), f = 100 MHz, T = 25°C; parameters specified differentially (in/out), unless otherwise noted. CD and RD are selected for differential broadband operation (see Table 5 and Table 6).
Table 1. Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE −3 dB Bandwidth AV = 6 dB, VOUT ≤ 1.0 V p-p 2500 MHz AV = 10 dB, VOUT ≤ 1.0 V p-p 2200 MHz AV = 14 dB, VOUT ≤ 1.0 V p-p 1800 MHz Bandwidth for 0.1 dB Flatness 3 dB ≤ AV ≤ 20 dB, VOUT ≤ 1.0 V p-p 190 MHz Bandwidth for 0.2 dB Flatness 3 dB ≤ AV ≤ 20 dB, VOUT ≤ 1.0 V p-p 300 MHz Gain Accuracy Using 1% resistor for RG, 0 dB ≤ AV ≤ 20 dB ±1 dB Gain Supply Sensitivity VS ± 5% 0.06 dB/V Gain Temperature Sensitivity −40°C to +85°C 4 mdB/°C Slew Rate RL = 1 kΩ, VOUT = 2 V step 9 V/ns RL = 200 Ω, VOUT = 2 V step 8 V/ns Settling Time 2 V step to 1% <2 ns Overdrive Recovery Time VIN = 4 V to 0 V step, VOUT ≤ ±10 mV <3 ns Reverse Isolation (S12) −80 dB INPUT/OUTPUT CHARACTERISTICS Common-Mode Nominal VCC/2 V Voltage Adjustment Range 1.2 to 3.8 V Maximum Output Voltage Swing 1 dB compressed 6 V p-p Output Common-Mode Offset Referenced to VCC/2 −100 +20 mV Output Common-Mode Drift −40°C to +85°C 0.25 mV/°C Output Differential Offset Voltage −20 +20 mV Common-Mode Rejection Ratio (CMRR) 57 dB Output Differential Offset Drift −40°C to +85°C 0.15 mV/°C Input Bias Current ±5 µA Input Resistance 3 kΩ Input Capacitance (Single Ended) 0.9 pF Output Resistance 100 Ω Output Capacitance 3 pF POWER INTERFACE Supply Voltage 3 5 5.5 V ENB Threshold 1.5 V ENB Input Bias Current ENB at 3 V 75 nA ENB at 0.6 V −125 µA Quiescent Current ENB at 3 V 35 37 39 mA ENB at 0.6 V 5.3 mA Rev. C | Page 3 of 19 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS NOISE DISTORTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GAIN AND DISTORTION ADJUSTMENT (DIFFERENTIAL INPUT) SINGLE-ENDED INPUT OPERATION NARROW-BAND, THIRD-ORDER INTERMODULATION CANCELLATION HIGH PERFORMANCE ADC DRIVING LAYOUT AND TRANSMISSION LINE EFFECTS EVALUATION BOARD EVALUATION BOARD LOADING SCHEMES SOLDERING INFORMATION EVALUATION BOARD SCHEMATICS OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD8352 SPECIFICATIONS
VS = 5 V, RL = 200 Ω differential, RG = 118 Ω (AV = 10 dB), f = 100 MHz, T = 25°C; parameters specified differentially (in/out), unless otherwise noted. CD and RD are selected for differential broadband operation (see Table 5 and Table 6).
Table 1. Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE −3 dB Bandwidth AV = 6 dB, VOUT ≤ 1.0 V p-p 2500 MHz AV = 10 dB, VOUT ≤ 1.0 V p-p 2200 MHz AV = 14 dB, VOUT ≤ 1.0 V p-p 1800 MHz Bandwidth for 0.1 dB Flatness 3 dB ≤ AV ≤ 20 dB, VOUT ≤ 1.0 V p-p 190 MHz Bandwidth for 0.2 dB Flatness 3 dB ≤ AV ≤ 20 dB, VOUT ≤ 1.0 V p-p 300 MHz Gain Accuracy Using 1% resistor for RG, 0 dB ≤ AV ≤ 20 dB ±1 dB Gain Supply Sensitivity VS ± 5% 0.06 dB/V Gain Temperature Sensitivity −40°C to +85°C 4 mdB/°C Slew Rate RL = 1 kΩ, VOUT = 2 V step 9 V/ns RL = 200 Ω, VOUT = 2 V step 8 V/ns Settling Time 2 V step to 1% <2 ns Overdrive Recovery Time VIN = 4 V to 0 V step, VOUT ≤ ±10 mV <3 ns Reverse Isolation (S12) −80 dB INPUT/OUTPUT CHARACTERISTICS Common-Mode Nominal VCC/2 V Voltage Adjustment Range 1.2 to 3.8 V Maximum Output Voltage Swing 1 dB compressed 6 V p-p Output Common-Mode Offset Referenced to VCC/2 −100 +20 mV Output Common-Mode Drift −40°C to +85°C 0.25 mV/°C Output Differential Offset Voltage −20 +20 mV Common-Mode Rejection Ratio (CMRR) 57 dB Output Differential Offset Drift −40°C to +85°C 0.15 mV/°C Input Bias Current ±5 µA Input Resistance 3 kΩ Input Capacitance (Single Ended) 0.9 pF Output Resistance 100 Ω Output Capacitance 3 pF POWER INTERFACE Supply Voltage 3 5 5.5 V ENB Threshold 1.5 V ENB Input Bias Current ENB at 3 V 75 nA ENB at 0.6 V −125 µA Quiescent Current ENB at 3 V 35 37 39 mA ENB at 0.6 V 5.3 mA Rev. C | Page 3 of 19 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS NOISE DISTORTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GAIN AND DISTORTION ADJUSTMENT (DIFFERENTIAL INPUT) SINGLE-ENDED INPUT OPERATION NARROW-BAND, THIRD-ORDER INTERMODULATION CANCELLATION HIGH PERFORMANCE ADC DRIVING LAYOUT AND TRANSMISSION LINE EFFECTS EVALUATION BOARD EVALUATION BOARD LOADING SCHEMES SOLDERING INFORMATION EVALUATION BOARD SCHEMATICS OUTLINE DIMENSIONS ORDERING GUIDE