Datasheet AD8366 (Analog Devices) - 4

AD8366 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
10 MHz Noise Figure Maximum gain 11.4 dB Minimum gain 18 dB Second Harmonic 2 V p-p output, maximum gain −97 dBc 2 V p-p output, minimum gain −96 dBc Third Harmonic 2 V p-p output, maximum gain −97 dBc 2 V p-p output, minimum gain −90 dBc OIP31 2 V p-p composite, maximum gain 38 dBVrms 2 V p-p composite, minimum gain 36 dBVrms OIP21 2 V p-p composite, maximum gain 72 dBVrms 2 V p-p composite, minimum gain 76 dBVrms Output 1 dB Compression Point1 Maximum gain 7 dBVrms Minimum gain 6.7 dBVrms 50 MHz Noise Figure Maximum gain 11.8 dB Minimum gain 18.2 dB Second Harmonic 2 V p-p output, maximum gain −82 dBc 2 V p-p output, minimum gain −84 dBc Third Harmonic 2 V p-p output, maximum gain −80 dBc 2 V p-p output, minimum gain −71 dBc OIP31 2 V p-p composite, maximum gain 32 dBVrms 2 V p-p composite, minimum gain 26 dBVrms OIP21 2 V p-p composite, maximum gain 71 dBVrms 2 V p-p composite, minimum gain 78 dBVrms Output 1 dB Compression Point1 Maximum gain 6.7 dBVrms Minimum gain 6.7 dBVrms DIGITAL LOGIC SENB, DENA, DENB, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5 Input High Voltage, VINH 2.2 V Input Low Voltage, VINL 1.2 V Input Capacitance, CIN 1 pF Input Resistance, RIN 50 kΩ SPI INTERFACE TIMING SENB = high fSCLK Serial clock frequency (maximum) 44.4 MHz t1 CS rising edge to first SCLK rising edge (minimum) 7.5 ns t2 SCLK high pulse width (minimum) 7.5 ns t3 SCLK low pulse width (minimum) 15 ns t4 SCLK falling edge to CS low (minimum) 7.5 ns t5 SDAT setup time (minimum) 7.5 ns t6 SDAT hold time (minimum) 15 ns PARALLEL PORT TIMING SENB = low t7 DENA/DENB high pulse width (minimum) 7.5 ns t8 DENA/DENB low pulse width (minimum) 15 ns t9 BITx setup time (minimum) 7.5 ns t10 BITx hold time (minimum) 7.5 ns POWER AND ENABLE VPSIA, VPSIB, VPSOA, VPSOB, ICOM, OCOM, ENBL Supply Voltage Range 4.75 5.25 V Total Supply Current ENBL = 5 V 180 mA Disable Current ENBL = 0 V 3.2 mA Disable Threshold 1.65 V Enable Response Time Delay following high-to-low transition until device 150 ns meets full specifications Disable Response Time Delay following low-to-high transition until device 3 µs produces full attenuation 1 To convert to dBm for a 200 Ω load impedance, add 7 dB to the dBVrms value. Rev. B | Page 4 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS PARALLEL AND SERIAL INTERFACE TIMING ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION INPUTS OUTPUTS OUTPUT DIFFERENTIAL OFFSET CORRECTION OUTPUT COMMON-MODE CONTROL GAIN CONTROL INTERFACE APPLICATIONS INFORMATION BASIC CONNECTIONS DIRECT CONVERSION RECEIVER DESIGN QUADRATURE ERRORS AND IMAGE REJECTION LOW FREQUENCY IMD3 PERFORMANCE BASEBAND INTERFACE CHARACTERIZATION SETUPS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE