Datasheet LT1777 (Analog Devices) - 8

LT1777
U OPERATIO
The LT1777 is a current mode step-down switcher regu- coupled with small-valued capacitor C1 to the VIN supply lator IC designed for low noise operation. The Block rail. The product of negative voltage slew rate times this Diagram shows an overall view of the system. The indi- capacitor value equals current, and when this current vidual blocks are straightforward and similar to those through emitter/base resistor R1 exceeds a diode drop, Q3 found in traditional designs, including: Internal Bias Regu- and then Q4 turn on supplying base drive to output device lator, Oscillator, Logic, and Feedback Amplifier. The novel Q1 to limit – dV/dt rate. portion includes a specialized Output Switch section in- In addition to voltage rates, the current slew rate also cluding circuits to limit the dI/dt and dV/dt switching rates. needs to be controlled for reduced noise behavior. This is The LT1777 operates much the same as traditional current provided by the section in the Block Diagram labeled mode switchers, the major difference being its specialized “±dI/dt Limiter.” The details of this circuit can be seen in output switch section. Due to space constraints, this the Output Stage Simplified Schematic. Note that an extra, discussion will not reiterate the basics of current mode small-valued inductor, termed the “sense inductor” has switcher/controllers and the “buck” topology. A good been added to the classic buck topology. As this inductor source of information on these topics is Application Note is external to the LT1777, its value can be chosen by the AN19. user allowing for optimization on a per application basis. Operation of the current slew limiter is as follows: The A straightforward output stage is provided by current product of the sense inductor times the dI/dt through it source I1 driving the base of PNP transistor Q2. The generates a voltage according to the well known formula collector of Q2 in turn drives the base of NPN output device V = (L)(dI/dt). The remainder of the circuit is configured Q1. The considerable base/collector capacitance of PNP such that when the voltage across the sense inductor Q2 acts to limit dV/dt rate during switch turn-on. However, reaches ±2V when the switch is to be turned off, the only natural limit BE, drive current will be supplied or removed as necessary to limit current slew rate. The actual sensing to voltage slew rate would be the collector/base capaci- is performed between the output node labeled V tance of Q1 providing drive for the same device. While SW and a new node labeled V dependent upon output load level and Q1’s β, the turn-off D. voltage slew rate would be typically much faster than the In the case of switch turn-on, current drive is provided by turn-on rate. To limit the voltage slew rate on switch turn- PNP Q2. If the voltage at VSW reaches 2VBE above that at off, an extra function is supplied. This is denoted by the VD, transistor Q5 turns on and removes a portion of Q2’s block labeled “– dV/dt Limiter.” drive from Q1’s base. Similarly for turn-off, as the VSW node goes 2V The details of the – dV/dt Limiter can be seen in the Output BE below VD, transistor Q6 then turns on to drive Q1’s base as needed. The net effect is that of limiting Stage Simplified Schematic. Transistors Q3 and Q4 are the switch node dI/dt in both directions at a rate inversely connected in a Darlington configuration whose input is proportional to the external sense inductor value. 8