Datasheet LT3431 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | High Voltage, 3A, 500kHz Step-Down Switching Regulator |
| Páginas / Página | 28 / 6 — PI FU CTIO S. GND (Pins 1, 8, 9, 16):. C (Pin 11). FB (Pin 12):. SW (Pins … |
| Formato / tamaño de archivo | PDF / 263 Kb |
| Idioma del documento | Inglés |
PI FU CTIO S. GND (Pins 1, 8, 9, 16):. C (Pin 11). FB (Pin 12):. SW (Pins 2, 5):. VIN (Pins 3, 4):. SYNC (Pin 14):. SHDN (Pin 15):
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LT3431
U U U PI FU CTIO S GND (Pins 1, 8, 9, 16):
The GND pin connections act as supply. This architecture increases efficiency especially the reference for the regulated output, so load regulation when the input voltage is much higher than the output. will suffer if the “ground” end of the load is not at the same Minimum output voltage setting for this mode of operation voltage as the GND pins of the IC. This condition will occur is 3V. when load current or other currents flow through metal
V
paths between the GND pins and the load ground. Keep the
C (Pin 11)
The VC pin is the output of the error amplifier and the input of the peak switch current comparator. It is paths between the GND pins and the load ground short normally used for frequency compensation, but can also and use a ground plane when possible. The FE package has serve as a current clamp or control loop override. V an exposed pad that is fused to the GND pins. The pad C sits at about 0.9V for light loads and 2.1V at maximum load. It should be soldered to the copper ground plane under the can be driven to ground to shut off the regulator, but if device to reduce thermal resistance. (See Applications driven high, current must be limited to 4mA. Information—Layout Considerations.)
FB (Pin 12):
The feedback pin is used to set the output
SW (Pins 2, 5):
The switch pin is the emitter of the on-chip voltage using an external voltage divider that generates power NPN switch. This pin is driven up to the input pin 1.22V at the pin for the desired output voltage. Three voltage during switch on time. Inductor current drives the additional functions are performed by the FB pin. When the switch pin voltage negative during switch off time. Nega- pin voltage drops below 0.6V, switch current limit is tive voltage is clamped with the external catch diode. reduced and the external SYNC function is disabled. Below Maximum negative switch voltage allowed is – 0.8V. 0.8V, switching frequency is also reduced. See Feedback
VIN (Pins 3, 4):
This is the collector of the on-chip power Pin Functions in Applications Information for details. NPN switch. VIN powers the internal control circuitry when
SYNC (Pin 14):
The SYNC pin is used to synchronize the a voltage on the BIAS pin is not present. High dI/dt edges internal oscillator to an external signal. It is directly logic occur on this pin during switch turn on and off. Keep the compatible and can be driven with any signal between path short from the VIN pin through the input bypass 10% and 90% duty cycle. The synchronizing range is capacitor, through the catch diode back to SW. All trace equal to initial operating frequency up to 700kHz. See inductance in this path creates voltage spikes at switch off, Synchronizing in Applications Information for details. adding to the VCE voltage across the internal NPN.
SHDN (Pin 15):
The SHDN pin is used to turn off the
BOOST (Pin 6):
The BOOST pin is used to provide a drive regulator and to reduce input drain current to a few voltage, higher than the input voltage, to the internal bipo- microamperes. This pin has two thresholds: one at 2.38V lar NPN power switch. Without this added voltage, the to disable switching and a second at 0.4V to force com- typical switch voltage loss would be about 1.5V. The ad- plete micropower shutdown. The 2.38V threshold func- ditional BOOST voltage allows the switch to saturate and tions as an accurate undervoltage lockout (UVLO); some- voltage loss approximates that of a 0.1Ω FET structure. times used to prevent the regulator from delivering power
NC (Pins 7, 13):
No Connection. until the input voltage has reached a predetermined level.
BIAS (Pin 10):
The BIAS pin is used to improve efficiency If the SHDN pin functions are not required, the pin can when operating at higher input voltages and light load either be left open (to allow an internal bias current to lift current. Connecting this pin to the regulated output volt- the pin to a default high state) or be forced high to a level age forces most of the internal circuitry to draw its oper- not to exceed 6V. ating current from the output voltage rather than the input sn3431 3431fs 6
U U U PI FU CTIO S GND (Pins 1, 8, 9, 16):
The GND pin connections act as supply. This architecture increases efficiency especially the reference for the regulated output, so load regulation when the input voltage is much higher than the output. will suffer if the “ground” end of the load is not at the same Minimum output voltage setting for this mode of operation voltage as the GND pins of the IC. This condition will occur is 3V. when load current or other currents flow through metal
V
paths between the GND pins and the load ground. Keep the
C (Pin 11)
The VC pin is the output of the error amplifier and the input of the peak switch current comparator. It is paths between the GND pins and the load ground short normally used for frequency compensation, but can also and use a ground plane when possible. The FE package has serve as a current clamp or control loop override. V an exposed pad that is fused to the GND pins. The pad C sits at about 0.9V for light loads and 2.1V at maximum load. It should be soldered to the copper ground plane under the can be driven to ground to shut off the regulator, but if device to reduce thermal resistance. (See Applications driven high, current must be limited to 4mA. Information—Layout Considerations.)
FB (Pin 12):
The feedback pin is used to set the output
SW (Pins 2, 5):
The switch pin is the emitter of the on-chip voltage using an external voltage divider that generates power NPN switch. This pin is driven up to the input pin 1.22V at the pin for the desired output voltage. Three voltage during switch on time. Inductor current drives the additional functions are performed by the FB pin. When the switch pin voltage negative during switch off time. Nega- pin voltage drops below 0.6V, switch current limit is tive voltage is clamped with the external catch diode. reduced and the external SYNC function is disabled. Below Maximum negative switch voltage allowed is – 0.8V. 0.8V, switching frequency is also reduced. See Feedback
VIN (Pins 3, 4):
This is the collector of the on-chip power Pin Functions in Applications Information for details. NPN switch. VIN powers the internal control circuitry when
SYNC (Pin 14):
The SYNC pin is used to synchronize the a voltage on the BIAS pin is not present. High dI/dt edges internal oscillator to an external signal. It is directly logic occur on this pin during switch turn on and off. Keep the compatible and can be driven with any signal between path short from the VIN pin through the input bypass 10% and 90% duty cycle. The synchronizing range is capacitor, through the catch diode back to SW. All trace equal to initial operating frequency up to 700kHz. See inductance in this path creates voltage spikes at switch off, Synchronizing in Applications Information for details. adding to the VCE voltage across the internal NPN.
SHDN (Pin 15):
The SHDN pin is used to turn off the
BOOST (Pin 6):
The BOOST pin is used to provide a drive regulator and to reduce input drain current to a few voltage, higher than the input voltage, to the internal bipo- microamperes. This pin has two thresholds: one at 2.38V lar NPN power switch. Without this added voltage, the to disable switching and a second at 0.4V to force com- typical switch voltage loss would be about 1.5V. The ad- plete micropower shutdown. The 2.38V threshold func- ditional BOOST voltage allows the switch to saturate and tions as an accurate undervoltage lockout (UVLO); some- voltage loss approximates that of a 0.1Ω FET structure. times used to prevent the regulator from delivering power
NC (Pins 7, 13):
No Connection. until the input voltage has reached a predetermined level.
BIAS (Pin 10):
The BIAS pin is used to improve efficiency If the SHDN pin functions are not required, the pin can when operating at higher input voltages and light load either be left open (to allow an internal bias current to lift current. Connecting this pin to the regulated output volt- the pin to a default high state) or be forced high to a level age forces most of the internal circuitry to draw its oper- not to exceed 6V. ating current from the output voltage rather than the input sn3431 3431fs 6