Datasheet LTC3810 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 100V Current Mode Synchronous Switching Regulator Controller |
| Páginas / Página | 38 / 9 — PIN FUNCTIONS. ION (Pin 1):. PLL/LPF (Pin 10):. VON (Pin 4):. SS/TRACK … |
| Formato / tamaño de archivo | PDF / 491 Kb |
| Idioma del documento | Inglés |
PIN FUNCTIONS. ION (Pin 1):. PLL/LPF (Pin 10):. VON (Pin 4):. SS/TRACK (Pin 11):. SGND (Pin 12):. VRNG (Pin 5):. SHDN (Pin 13):
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LTC3810
PIN FUNCTIONS ION (Pin 1):
On-Time Current Input. Tie a resistor from VIN
PLL/LPF (Pin 10):
The phase-locked loop’s lowpass fi lter to this pin to set the one-shot timer current and thereby is tied to this pin. The voltage at this pin defaults to 1.2V set the switching frequency. when the IC is not synchronized with an external clock at the MODE/SYNC pin.
VON (Pin 4):
On-Time Voltage Input. Voltage trip point for the on-time comparator. Tying this pin to the output voltage
SS/TRACK (Pin 11):
Soft-Start/Tracking Input. For soft- or an external resistive divider from the output makes the start, a capacitor to ground at this pin sets the ramp rate of on-time proportional to VOUT. The comparator defaults to the output voltage (approximately 0.6s/μF). For coincident 0.7V when the pin is grounded and defaults to 2.4V when or ratiometric tracking, connect this pin to a resistive divider the pin is connected to INTVCC. Tie this pin to INTVCC in between the voltage to be tracked and ground. high VOUT applications to use a lower RON value.
SGND (Pin 12):
Signal Ground. All small-signal compo-
VRNG (Pin 5):
Sense Voltage Limit Set. The voltage at this nents should connect to this ground and eventually connect pin sets the nominal sense voltage at maximum output to PGND at one point. current and can be set from 0.5V to 2V by a resistive
SHDN (Pin 13):
Shutdown Pin. Pulling this pin below 1.5V divider from INTVCC. The nominal sense voltage defaults will shut down the LTC3810, turn off both of the external to 95mV when this pin is tied to ground, and 215mV when MOSFET switches and reduce the quiescent supply cur- tied to INTVCC. rent to 240μA.
PGOOD (Pin 6):
Power Good Output. Open-drain logic
UVIN (Pin 14):
UVLO Input. This pin is input to the internal output that is pulled to ground when the output voltage UVLO and is compared to an internal 0.8V reference. An is not between ±10% of the regulation point. The output external resistor divider is connected to this pin and the voltage must be out of regulation for at least 120μs before input supply to program the undervoltage lockout voltage. the power good output is pulled to ground. When UVIN is less than 0.8V, the LTC3810 is shut down.
MODE/SYNC (Pin 7):
Pulse Skip Mode Enable/Sync Pin.
NDRV (Pin 15):
Drive Output for External Pass Device of This multifunction pin provides pulse skip mode enable/ the Linear Regulator for INTV disable control and an external clock input to the phase CC. Connect to the gate of an external NMOS pass device and a pull-up resistor to detector. Pulling this pin below 0.8V or to an external the input voltage V logic-level synchronization signal disables pulse skip mode IN. operation and forces continuous operation. Pulling this
EXTVCC (Pin 16):
External Driver Supply Voltage. When pin above 0.8V enables pulse skip mode operation. For a this voltage exceeds 6.7V, an internal switch connects clock input, the phase-locked loop will force the rising top this pin to INTVCC through an LDO and turns off the exter- gate signal to be synchronized with the rising edge of the nal MOSFET connected to NDRV, so that controller and clock signal.This pin can also be connected to a feedback gate drive are drawn from EXTVCC. resistor divider from a secondary winding on the inductor
INTVCC (Pin 17):
Main Supply Pin. All internal circuits to regulate a second output voltage. except the output drivers are powered from this pin.
I
INTV
TH (Pin 8):
Error Amplifi er Compensation Point and Cur- CC should be bypassed to ground (Pin 10) with at rent Control Threshold. The current comparator threshold least a 0.1μF capacitor in close proximity to the LTC3810. increases with control voltage. The voltage ranges from
DRVCC (Pin 18):
Driver Supply Pin. DRVCC supplies power 0V to 2.6V with 1.2V corresponding to zero sense voltage to the BG output driver. This pin is normally connected to (zero current). INTVCC. DRVCC should be bypassed to BGRTN (Pin 20)
V
with a low ESR (X5R or better) 1μF capacitor in close
FB (Pin 9):
Feedback Input. Connect VFB through a resistor divider network to V proximity to the LTC3810. OUT to set the output voltage. 3810fc 9
PIN FUNCTIONS ION (Pin 1):
On-Time Current Input. Tie a resistor from VIN
PLL/LPF (Pin 10):
The phase-locked loop’s lowpass fi lter to this pin to set the one-shot timer current and thereby is tied to this pin. The voltage at this pin defaults to 1.2V set the switching frequency. when the IC is not synchronized with an external clock at the MODE/SYNC pin.
VON (Pin 4):
On-Time Voltage Input. Voltage trip point for the on-time comparator. Tying this pin to the output voltage
SS/TRACK (Pin 11):
Soft-Start/Tracking Input. For soft- or an external resistive divider from the output makes the start, a capacitor to ground at this pin sets the ramp rate of on-time proportional to VOUT. The comparator defaults to the output voltage (approximately 0.6s/μF). For coincident 0.7V when the pin is grounded and defaults to 2.4V when or ratiometric tracking, connect this pin to a resistive divider the pin is connected to INTVCC. Tie this pin to INTVCC in between the voltage to be tracked and ground. high VOUT applications to use a lower RON value.
SGND (Pin 12):
Signal Ground. All small-signal compo-
VRNG (Pin 5):
Sense Voltage Limit Set. The voltage at this nents should connect to this ground and eventually connect pin sets the nominal sense voltage at maximum output to PGND at one point. current and can be set from 0.5V to 2V by a resistive
SHDN (Pin 13):
Shutdown Pin. Pulling this pin below 1.5V divider from INTVCC. The nominal sense voltage defaults will shut down the LTC3810, turn off both of the external to 95mV when this pin is tied to ground, and 215mV when MOSFET switches and reduce the quiescent supply cur- tied to INTVCC. rent to 240μA.
PGOOD (Pin 6):
Power Good Output. Open-drain logic
UVIN (Pin 14):
UVLO Input. This pin is input to the internal output that is pulled to ground when the output voltage UVLO and is compared to an internal 0.8V reference. An is not between ±10% of the regulation point. The output external resistor divider is connected to this pin and the voltage must be out of regulation for at least 120μs before input supply to program the undervoltage lockout voltage. the power good output is pulled to ground. When UVIN is less than 0.8V, the LTC3810 is shut down.
MODE/SYNC (Pin 7):
Pulse Skip Mode Enable/Sync Pin.
NDRV (Pin 15):
Drive Output for External Pass Device of This multifunction pin provides pulse skip mode enable/ the Linear Regulator for INTV disable control and an external clock input to the phase CC. Connect to the gate of an external NMOS pass device and a pull-up resistor to detector. Pulling this pin below 0.8V or to an external the input voltage V logic-level synchronization signal disables pulse skip mode IN. operation and forces continuous operation. Pulling this
EXTVCC (Pin 16):
External Driver Supply Voltage. When pin above 0.8V enables pulse skip mode operation. For a this voltage exceeds 6.7V, an internal switch connects clock input, the phase-locked loop will force the rising top this pin to INTVCC through an LDO and turns off the exter- gate signal to be synchronized with the rising edge of the nal MOSFET connected to NDRV, so that controller and clock signal.This pin can also be connected to a feedback gate drive are drawn from EXTVCC. resistor divider from a secondary winding on the inductor
INTVCC (Pin 17):
Main Supply Pin. All internal circuits to regulate a second output voltage. except the output drivers are powered from this pin.
I
INTV
TH (Pin 8):
Error Amplifi er Compensation Point and Cur- CC should be bypassed to ground (Pin 10) with at rent Control Threshold. The current comparator threshold least a 0.1μF capacitor in close proximity to the LTC3810. increases with control voltage. The voltage ranges from
DRVCC (Pin 18):
Driver Supply Pin. DRVCC supplies power 0V to 2.6V with 1.2V corresponding to zero sense voltage to the BG output driver. This pin is normally connected to (zero current). INTVCC. DRVCC should be bypassed to BGRTN (Pin 20)
V
with a low ESR (X5R or better) 1μF capacitor in close
FB (Pin 9):
Feedback Input. Connect VFB through a resistor divider network to V proximity to the LTC3810. OUT to set the output voltage. 3810fc 9